/** @file
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*
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* Copyright (c) 2017, Linaro, Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <PiDxe.h>
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#include <Guid/ArmMpCoreInfo.h>
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#include <libfdt.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DxeServicesLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PrintLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/AmdMpCoreInfo.h>
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#include <SocVersion.h>
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#define PMU_INT_FLAG_SPI 0
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#define PMU_INT_TYPE_HIGH_LEVEL 4
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#define NUM_CORES FixedPcdGet32 (PcdCoreCount)
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//
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// PMU interrupts per core
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//
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#pragma pack(push, 1)
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typedef struct {
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UINT32 Flag; // 0 == SPI
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UINT32 IntId; // GSIV == IntId+32
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UINT32 Type; // 4 == Level-Sensitive, Active-High
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} PMU_INTERRUPT;
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#pragma pack(pop)
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STATIC
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BOOLEAN
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ClusterInRange (
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IN ARM_CORE_INFO *ArmCoreInfoTable,
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IN UINTN ClusterId,
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IN UINTN LowIndex,
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IN UINTN HighIndex
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)
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{
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do {
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if (ClusterId == ArmCoreInfoTable[LowIndex].ClusterId)
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return TRUE;
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} while (++LowIndex <= HighIndex);
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return FALSE;
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}
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STATIC
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UINTN
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NumberOfCoresInCluster (
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IN ARM_CORE_INFO *ArmCoreInfoTable,
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IN UINTN NumberOfEntries,
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IN UINTN ClusterId
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)
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{
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UINTN Index, Cores;
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Cores = 0;
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for (Index = 0; Index < NumberOfEntries; ++Index) {
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if (ClusterId == ArmCoreInfoTable[Index].ClusterId)
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++Cores;
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}
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return Cores;
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}
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STATIC
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UINTN
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NumberOfClustersInTable (
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IN ARM_CORE_INFO *ArmCoreInfoTable,
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IN UINTN NumberOfEntries
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)
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{
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UINTN Index, Cores, Clusters, ClusterId;
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Index = 0;
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Clusters = 0;
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Cores = NumberOfEntries;
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while (Cores) {
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++Clusters;
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ClusterId = ArmCoreInfoTable[Index].ClusterId;
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Cores -= NumberOfCoresInCluster (ArmCoreInfoTable,
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NumberOfEntries,
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ClusterId);
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if (Cores) {
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do {
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++Index;
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} while (ClusterInRange (ArmCoreInfoTable,
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ArmCoreInfoTable[Index].ClusterId,
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0, Index-1));
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}
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}
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return Clusters;
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}
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STATIC
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INT32
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fdt_alloc_phandle (
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IN VOID *Fdt
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)
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{
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INT32 Offset;
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INT32 Phandle;
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Phandle = 0;
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for (Offset = fdt_next_node (Fdt, -1, NULL); Offset >= 0;
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Offset = fdt_next_node (Fdt, Offset, NULL)) {
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Phandle = MAX (Phandle, fdt_get_phandle (Fdt, Offset));
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}
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return Phandle + 1;
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}
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STATIC
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VOID
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SetDeviceStatus (
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IN VOID *Fdt,
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IN CONST CHAR8 *Device,
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IN BOOLEAN Enable
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)
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{
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INT32 Node;
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INT32 SubNode;
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INT32 Rc;
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Node = fdt_subnode_offset (Fdt, 0, "smb");
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if (Node >= 0) {
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SubNode = fdt_subnode_offset (Fdt, Node, Device);
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if (SubNode >= 0) {
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Rc = fdt_setprop_string (Fdt, SubNode, "status",
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Enable ? "okay" : "disabled");
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if (Rc) {
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DEBUG ((DEBUG_ERROR,
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"%a: Could not set 'status' property for '%a' node\n",
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__FUNCTION__, Device));
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}
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}
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}
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}
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#define MAC_ADDRESS_BYTES 6
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STATIC
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VOID
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SetMacAddress (
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IN VOID *Fdt,
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IN CONST CHAR8 *Device,
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IN UINT8 *MacAddress
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)
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{
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INT32 Node;
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INT32 SubNode;
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INT32 Rc;
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Node = fdt_subnode_offset (Fdt, 0, "smb");
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if (Node >= 0) {
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SubNode = fdt_subnode_offset (Fdt, Node, Device);
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if (SubNode >= 0) {
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Rc = fdt_setprop (Fdt, SubNode, "mac-address", MacAddress,
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MAC_ADDRESS_BYTES);
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if (Rc) {
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DEBUG ((DEBUG_ERROR,
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"%a: Could not set 'mac-address' property for '%a' node\n",
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__FUNCTION__, Device));
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}
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}
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}
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}
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STATIC
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VOID
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DisableSmmu (
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IN VOID *Fdt,
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IN CONST CHAR8 *IommuPropName,
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IN CONST CHAR8 *SmmuNodeName,
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IN CONST CHAR8 *DeviceNodeName
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)
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{
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INT32 Node;
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INT32 Error;
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Node = fdt_path_offset (Fdt, DeviceNodeName);
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if (Node <= 0) {
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DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n",
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__FUNCTION__, DeviceNodeName, fdt_strerror (Node)));
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return;
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}
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Error = fdt_delprop (Fdt, Node, IommuPropName);
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if (Error != 0) {
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DEBUG ((DEBUG_WARN, "%a: Failed to delete property %a: %a\n",
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__FUNCTION__, IommuPropName, fdt_strerror (Error)));
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return;
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}
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Node = fdt_path_offset (Fdt, SmmuNodeName);
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if (Node <= 0) {
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return;
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}
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Error = fdt_del_node (Fdt, Node);
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if (Error != 0) {
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DEBUG ((DEBUG_WARN, "%a: Failed to delete node %a: %a\n",
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__FUNCTION__, SmmuNodeName, fdt_strerror (Error)));
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}
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}
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STATIC
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VOID
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SetSocIdStatus (
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IN VOID *Fdt
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)
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{
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UINT32 SocId;
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BOOLEAN IsRevB1;
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SocId = PcdGet32 (PcdSocCpuId);
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IsRevB1 = (SocId & STYX_SOC_VERSION_MASK) >= STYX_SOC_VERSION_B1;
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SetDeviceStatus (Fdt, "sata@e0d00000",
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IsRevB1 && FixedPcdGet8 (PcdSata1PortCount) > 0);
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SetDeviceStatus (Fdt, "gpio@e0020000", IsRevB1);
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SetDeviceStatus (Fdt, "gpio@e0030000", IsRevB1);
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SetDeviceStatus (Fdt, "gwdt@e0bb0000", IsRevB1);
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if (FixedPcdGetBool (PcdEnableKcs)) {
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SetDeviceStatus (Fdt, "kcs@e0010000", IsRevB1);
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} else {
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SetDeviceStatus (Fdt, "kcs@e0010000", FALSE);
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}
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if (!PcdGetBool (PcdEnableSmmus)) {
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DisableSmmu (Fdt, "iommu-map", "/smb/smmu@e0a00000", "/smb/pcie@f0000000");
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DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000");
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DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/ccp@e0100000");
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DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000");
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}
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if (!FixedPcdGetBool (PcdXgbeEnable) || !PcdGetBool (PcdEnableSmmus)) {
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DisableSmmu (Fdt, "iommus", "/smb/smmu@e0600000", "/smb/xgmac@e0700000");
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DisableSmmu (Fdt, "iommus", "/smb/smmu@e0800000", "/smb/xgmac@e0900000");
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}
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}
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STATIC
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VOID
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SetXgbeStatus (
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IN VOID *Fdt
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)
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{
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if (FixedPcdGetBool (PcdXgbeEnable)) {
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SetDeviceStatus (Fdt, "xgmac@e0700000", TRUE);
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SetDeviceStatus (Fdt, "phy@e1240800", TRUE);
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SetDeviceStatus (Fdt, "xgmac@e0900000", TRUE);
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SetDeviceStatus (Fdt, "phy@e1240c00", TRUE);
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SetMacAddress (Fdt, "xgmac@e0700000", PcdGetPtr (PcdEthMacA));
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SetMacAddress (Fdt, "xgmac@e0900000", PcdGetPtr (PcdEthMacB));
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} else {
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SetDeviceStatus (Fdt, "xgmac@e0700000", FALSE);
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SetDeviceStatus (Fdt, "phy@e1240800", FALSE);
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SetDeviceStatus (Fdt, "xgmac@e0900000", FALSE);
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SetDeviceStatus (Fdt, "phy@e1240c00", FALSE);
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}
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}
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STATIC CONST CHAR8 mCpuCompatible[] = "arm,cortex-a57\0arm,armv8";
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STATIC CONST CHAR8 mPmuCompatible[] = "arm,cortex-a57-pmu\0arm,armv8-pmuv3";
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STATIC
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EFI_STATUS
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PrepareFdt (
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IN OUT VOID *Fdt,
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IN UINTN FdtSize
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)
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{
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EFI_STATUS Status;
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INT32 Node;
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INT32 CpuNode;
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UINTN Index;
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ARM_CORE_INFO *ArmCoreInfoTable;
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UINTN ArmCoreCount;
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INT32 MapNode;
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INT32 ClusterNode;
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INT32 PmuNode;
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PMU_INTERRUPT PmuInt;
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INT32 Phandle[NUM_CORES];
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UINT32 ClusterIndex;
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UINT32 CoreIndex;
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UINT32 ClusterCount;
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UINT32 CoresInCluster;
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UINT32 ClusterId;
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INT32 L2Node;
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INT32 L3Node;
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INT32 L2Phandle[NUM_CORES / 2];
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INT32 L3Phandle;
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UINTN MpId;
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CHAR8 Name[10];
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AMD_MP_CORE_INFO_PROTOCOL *AmdMpCoreInfoProtocol;
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//
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// Setup Arm Mpcore Info if it is a multi-core or multi-cluster platforms.
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//
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// For 'cpus' and 'cpu' device tree nodes bindings, refer to this file
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// in the kernel documentation:
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// Documentation/devicetree/bindings/arm/cpus.txt
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//
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Status = gBS->LocateProtocol (
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&gAmdMpCoreInfoProtocolGuid,
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NULL,
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(VOID **)&AmdMpCoreInfoProtocol
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);
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ASSERT_EFI_ERROR (Status);
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// Get pointer to ARM core info table
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ArmCoreInfoTable = AmdMpCoreInfoProtocol->GetArmCoreInfoTable (&ArmCoreCount);
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ASSERT (ArmCoreInfoTable != NULL);
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ASSERT (ArmCoreCount <= NUM_CORES);
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// Create the L3 cache node
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L3Node = fdt_add_subnode (Fdt, 0, "l3cache");
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if (L3Node < 0) {
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DEBUG ((DEBUG_ERROR, "FDT: Error creating 'l3cache' node\n"));
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return EFI_INVALID_PARAMETER;
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}
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L3Phandle = fdt_alloc_phandle (Fdt);
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fdt_setprop_cell (Fdt, L3Node, "cache-level", 3);
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fdt_setprop_cell (Fdt, L3Node, "cache-size", SIZE_8MB);
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fdt_setprop_cell (Fdt, L3Node, "cache-line-size", 64);
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fdt_setprop_cell (Fdt, L3Node, "cache-sets", 8192);
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fdt_setprop_empty (Fdt, L3Node, "cache-unified");
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fdt_setprop_cell (Fdt, L3Node, "phandle", L3Phandle);
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ClusterCount = NumberOfClustersInTable (ArmCoreInfoTable, ArmCoreCount);
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ASSERT (ClusterCount <= ARRAY_SIZE (L2Phandle));
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for (Index = 0; Index < ClusterCount; Index++) {
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AsciiSPrint (Name, sizeof (Name), "l2cache%d", Index);
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L2Node = fdt_add_subnode (Fdt, 0, Name);
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if (L2Node < 0) {
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DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name));
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return EFI_INVALID_PARAMETER;
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}
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L2Phandle[Index] = fdt_alloc_phandle (Fdt);
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fdt_setprop_cell (Fdt, L2Node, "cache-size", SIZE_1MB);
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fdt_setprop_cell (Fdt, L2Node, "cache-line-size", 64);
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fdt_setprop_cell (Fdt, L2Node, "cache-sets", 1024);
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fdt_setprop_empty (Fdt, L2Node, "cache-unified");
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fdt_setprop_cell (Fdt, L2Node, "next-level-cache", L3Phandle);
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fdt_setprop_cell (Fdt, L2Node, "phandle", L2Phandle[Index]);
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}
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// Get Id from primary CPU
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MpId = (UINTN)ArmReadMpidr ();
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// Create /cpus noide
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Node = fdt_add_subnode (Fdt, 0, "cpus");
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if (Node >= 0) {
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// Configure the 'cpus' node
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fdt_setprop_string (Fdt, Node, "name", "cpus");
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fdt_setprop_cell (Fdt, Node, "#address-cells", sizeof (UINTN) / 4);
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fdt_setprop_cell (Fdt, Node, "#size-cells", 0);
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} else {
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DEBUG ((DEBUG_ERROR, "FDT: Error creating 'cpus' node\n"));
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return EFI_INVALID_PARAMETER;
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}
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//
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// Walk the processor table in reverse order for proper listing in FDT
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//
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Index = ArmCoreCount;
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while (Index--) {
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// Create 'cpu' node
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AsciiSPrint (Name, sizeof (Name), "CPU%d", Index);
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CpuNode = fdt_add_subnode (Fdt, Node, Name);
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if (CpuNode < 0) {
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DEBUG ((DEBUG_ERROR, "FDT: Error on creating '%a' node\n", Name));
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return EFI_INVALID_PARAMETER;
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}
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Phandle[Index] = fdt_alloc_phandle (Fdt);
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fdt_setprop_cell (Fdt, CpuNode, "phandle", Phandle[Index]);
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fdt_setprop_string (Fdt, CpuNode, "enable-method", "psci");
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MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId,
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ArmCoreInfoTable[Index].CoreId);
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MpId = cpu_to_fdt64 (MpId);
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fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId));
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fdt_setprop (Fdt, CpuNode, "compatible", mCpuCompatible,
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sizeof (mCpuCompatible));
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fdt_setprop_string (Fdt, CpuNode, "device_type", "cpu");
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fdt_setprop_cell (Fdt, CpuNode, "i-cache-size", 3 * SIZE_16KB);
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fdt_setprop_cell (Fdt, CpuNode, "i-cache-line-size", 64);
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fdt_setprop_cell (Fdt, CpuNode, "i-cache-sets", 256);
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fdt_setprop_cell (Fdt, CpuNode, "d-cache-size", 2 * SIZE_16KB);
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fdt_setprop_cell (Fdt, CpuNode, "d-cache-line-size", 64);
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fdt_setprop_cell (Fdt, CpuNode, "d-cache-sets", 256);
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fdt_setprop_cell (Fdt, CpuNode, "l2-cache",
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L2Phandle[ArmCoreInfoTable[Index].ClusterId]);
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}
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// Create /cpu-map node
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MapNode = fdt_add_subnode (Fdt, Node, "cpu-map");
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if (MapNode >= 0) {
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ClusterIndex = ArmCoreCount - 1;
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ClusterCount = NumberOfClustersInTable (ArmCoreInfoTable,
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ArmCoreCount);
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while (ClusterCount--) {
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// Create 'cluster' node
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AsciiSPrint (Name, sizeof (Name), "cluster%d", ClusterCount);
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ClusterNode = fdt_add_subnode (Fdt, MapNode, Name);
|
if (ClusterNode < 0) {
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DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name));
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return EFI_INVALID_PARAMETER;
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}
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ClusterId = ArmCoreInfoTable[ClusterIndex].ClusterId;
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CoreIndex = ClusterIndex;
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CoresInCluster = NumberOfCoresInCluster (ArmCoreInfoTable,
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ArmCoreCount,
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ClusterId);
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while (CoresInCluster--) {
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// Create 'core' node
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AsciiSPrint (Name, sizeof (Name), "core%d", CoresInCluster);
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CpuNode = fdt_add_subnode (Fdt, ClusterNode, Name);
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if (CpuNode < 0) {
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DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name));
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return EFI_INVALID_PARAMETER;
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}
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fdt_setprop_cell (Fdt, CpuNode, "cpu", Phandle[CoreIndex]);
|
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// iterate to next core in cluster
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if (CoresInCluster) {
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do {
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--CoreIndex;
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} while (ClusterId != ArmCoreInfoTable[CoreIndex].ClusterId);
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}
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}
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// iterate to next cluster
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if (ClusterCount) {
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do {
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--ClusterIndex;
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} while (ClusterInRange (ArmCoreInfoTable,
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ArmCoreInfoTable[ClusterIndex].ClusterId,
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ClusterIndex + 1,
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ArmCoreCount - 1));
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}
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}
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} else {
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DEBUG ((DEBUG_ERROR,"FDT: Error creating 'cpu-map' node\n"));
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return EFI_INVALID_PARAMETER;
|
}
|
|
// Create /pmu node
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PmuNode = fdt_add_subnode(Fdt, 0, "pmu");
|
if (PmuNode >= 0) {
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fdt_setprop (Fdt, PmuNode, "compatible", mPmuCompatible,
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sizeof (mPmuCompatible));
|
|
// append PMU interrupts
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for (Index = 0; Index < ArmCoreCount; Index++) {
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MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId,
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ArmCoreInfoTable[Index].CoreId);
|
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Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR,
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"FDT: Error getting PMU interrupt for MpId '0x%x'\n", MpId));
|
return Status;
|
}
|
|
PmuInt.Flag = cpu_to_fdt32 (PMU_INT_FLAG_SPI);
|
PmuInt.IntId = cpu_to_fdt32 (PmuInt.IntId);
|
PmuInt.Type = cpu_to_fdt32 (PMU_INT_TYPE_HIGH_LEVEL);
|
fdt_appendprop (Fdt, PmuNode, "interrupts", &PmuInt, sizeof(PmuInt));
|
fdt_appendprop_cell (Fdt, PmuNode, "interrupt-affinity", Phandle[Index]);
|
}
|
} else {
|
DEBUG ((DEBUG_ERROR, "FDT: Error creating 'pmu' node\n"));
|
return EFI_INVALID_PARAMETER;
|
}
|
|
SetSocIdStatus (Fdt);
|
SetXgbeStatus (Fdt);
|
|
// Update the real size of the Device Tree
|
fdt_pack (Fdt);
|
|
return EFI_SUCCESS;
|
}
|
|
|
/**
|
Return a pool allocated copy of the DTB image that is appropriate for
|
booting the current platform via DT.
|
|
@param[out] Dtb Pointer to the DTB copy
|
@param[out] DtbSize Size of the DTB copy
|
|
@retval EFI_SUCCESS Operation completed successfully
|
@retval EFI_NOT_FOUND No suitable DTB image could be located
|
@retval EFI_OUT_OF_RESOURCES No pool memory available
|
|
**/
|
EFI_STATUS
|
EFIAPI
|
DtPlatformLoadDtb (
|
OUT VOID **Dtb,
|
OUT UINTN *DtbSize
|
)
|
{
|
EFI_STATUS Status;
|
VOID *OrigDtb;
|
VOID *CopyDtb;
|
UINTN OrigDtbSize;
|
UINTN CopyDtbSize;
|
INT32 Error;
|
|
Status = GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid,
|
EFI_SECTION_RAW, 0, &OrigDtb, &OrigDtbSize);
|
if (EFI_ERROR (Status)) {
|
return EFI_NOT_FOUND;
|
}
|
|
//
|
// Allocate space for the DTB: add a page of slack space to make some room
|
// for our modifications.
|
//
|
CopyDtbSize = OrigDtbSize + EFI_PAGE_SIZE;
|
CopyDtb = AllocatePool (CopyDtbSize);
|
if (CopyDtb == NULL) {
|
return EFI_OUT_OF_RESOURCES;
|
}
|
|
Error = fdt_open_into (OrigDtb, CopyDtb, CopyDtbSize);
|
if (Error != 0) {
|
//
|
// fdt_open_into() validates the DTB header, so if it fails, the template
|
// is most likely invalid.
|
//
|
return EFI_NOT_FOUND;
|
}
|
|
Status = PrepareFdt (CopyDtb, CopyDtbSize);
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
|
*Dtb = CopyDtb;
|
*DtbSize = CopyDtbSize;
|
|
return EFI_SUCCESS;
|
}
|
