/** @file
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SSDT for peripherals that are only enabled on B1 silicon
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Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
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Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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DefinitionBlock ("SsdtB1.aml", "SSDT", 2, "AMDINC", "StyxB1 ", 3)
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{
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Scope (_SB)
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{
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Device (AHC1)
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{
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Name (_HID, "AMDI0600") // _HID: Hardware ID
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Name (_UID, 0x01) // _UID: Unique ID
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Name (_CLS, Package (0x03) // _CLS: Class Code
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{
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0x01,
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0x06,
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0x01
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})
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Method (_STA)
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{
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If (LEqual (FixedPcdGet8 (PcdSata1PortCount), 0)) {
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Return (0x0)
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}
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Return (0xF)
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}
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE0D00000, // Address Base (MMIO)
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0x00010000, // Address Length
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)
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Memory32Fixed (ReadWrite,
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0xE000007C, // Address Base (SGPIO)
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0x00000001, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, }
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})
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}
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Device (GIO2)
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{
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Name (_HID, "AMDI0400") // _HID: Hardware ID
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Name (_CID, "ARMH0061") // _CID: Compatible ID
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Name (_UID, 0x02) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE0020000, // Address Base
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0x00001000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, }
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})
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}
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Device (GIO3)
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{
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Name (_HID, "AMDI0400") // _HID: Hardware ID
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Name (_CID, "ARMH0061") // _CID: Compatible ID
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Name (_UID, 0x03) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE0030000, // Address Base
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0x00001000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, }
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})
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}
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}
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}
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