/** @file
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Multiple APIC Description Table (MADT)
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Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
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Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <IndustryStandard/Acpi61.h>
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#include "AcpiPlatform.h"
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#define GICM_SPI_COUNT (0x100)
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#define GICM_SPI_BASE (0x40)
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#define GIC_BASE (FixedPcdGet64 (PcdGicInterruptInterfaceBase))
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#define GICD_BASE (FixedPcdGet64 (PcdGicDistributorBase))
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#define GICV_BASE (FixedPcdGet64 (PcdGicVirtualInterruptInterfaceBase))
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#define GICH_BASE (FixedPcdGet64 (PcdGicHypervisorInterruptInterfaceBase))
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#define VGIC_MAINT_INT (FixedPcdGet32 (PcdGicVirtualMaintenanceInterrupt))
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#define GICVR_BASE (FixedPcdGet64 (PcdGicVirtualRegisterInterfaceBase))
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#define GIC_MSI_FRAME (FixedPcdGet64 (PcdGicMSIFrameBase))
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#define GIC_VERSION (FixedPcdGet8 (PcdGicVersion))
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#define CORES_PER_CLUSTER (FixedPcdGet32 (PcdSocCoresPerCluster))
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/* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */
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#define AMD_GIC(CpuNum, ClusterId, CoreId, PerfInt) { \
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EFI_ACPI_5_1_GIC, /* UINT8 Type */ \
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sizeof (EFI_ACPI_5_1_GIC_STRUCTURE), /* UINT8 Length */ \
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EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved */ \
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CpuNum, /* UINT32 CPUInterfaceNumber */ \
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(ClusterId << 8) | CoreId, /* UINT32 AcpiProcessorUid */ \
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0, /* UINT32 Flags */ \
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0, /* UINT32 ParkingProtocolVersion */ \
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PerfInt, /* UINT32 PerformanceInterruptGsiv */ \
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0, /* UINT64 ParkedAddress */ \
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GIC_BASE, /* UINT64 PhysicalBaseAddress */ \
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GICV_BASE, /* UINT64 GICV */ \
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GICH_BASE, /* UINT64 GICH */ \
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VGIC_MAINT_INT, /* UINT32 VGICMaintenanceInterrupt */ \
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GICVR_BASE, /* UINT64 GICRBaseAddress */ \
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(ClusterId << 8) | CoreId /* UINT64 MPIDR */ \
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}
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#pragma pack(push, 1)
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typedef struct {
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EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
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EFI_ACPI_5_1_GIC_STRUCTURE GicC[MAX_CORES];
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EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE GicD;
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EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE GicM;
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} EFI_ACPI_5_1_ARM_MADT_STRUCTURE;
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#pragma pack(pop)
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STATIC EFI_ACPI_5_1_ARM_MADT_STRUCTURE AcpiMadt = {
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{
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AMD_ACPI_HEADER (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
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EFI_ACPI_5_1_ARM_MADT_STRUCTURE,
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EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
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GIC_BASE, // UINT32 LocalApicAddress
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0 // UINT32 Flags
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},
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{
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AMD_GIC (0, 0, 0, 39),
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AMD_GIC (1, 0, 1, 40),
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AMD_GIC (2, 1, 0, 41),
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AMD_GIC (3, 1, 1, 42),
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AMD_GIC (4, 2, 0, 43),
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AMD_GIC (5, 2, 1, 44),
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AMD_GIC (6, 3, 0, 45),
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AMD_GIC (7, 3, 1, 46),
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},
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/*
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* GIC Distributor
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*/
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{
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EFI_ACPI_5_1_GICD, // UINT8 Type
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sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE), // UINT8 Length
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EFI_ACPI_RESERVED_WORD, // UINT16 Reserved1
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0, // UINT32 GicId
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GICD_BASE, // UINT64 PhysicalBaseAddress
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0, // UINT32 SystemVectorBase
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EFI_ACPI_RESERVED_BYTE, // UINT8 GicVersion
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{ // UINT8 Reserved2[3]
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EFI_ACPI_RESERVED_BYTE,
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EFI_ACPI_RESERVED_BYTE,
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EFI_ACPI_RESERVED_BYTE,
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}
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},
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/*
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* GIC MSI Frame
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*/
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{
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EFI_ACPI_5_1_GIC_MSI_FRAME, // UINT8 Type
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sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE), // UINT8 Length
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EFI_ACPI_RESERVED_WORD, // UINT16 Reserved1
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0, // UINT32 GicMsiFrameId
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GIC_MSI_FRAME, // UINT64 PhysicalBaseAddress
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0, // UINT32 Flags
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GICM_SPI_COUNT, // UINT16 SPICount
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GICM_SPI_BASE // UINT16 SPIBase
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}
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};
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VOID* CONST ReferenceAcpiTable = &AcpiMadt;
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