/** @file
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Generic Timer Description Table (GTDT)
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Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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/**
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Derived from:
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ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc
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**/
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#include "AcpiPlatform.h"
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#pragma pack(push, 1)
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#define CNT_CONTROL_BASE_ADDRESS FixedPcdGet64(PcdCntControlBase)
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#define CNT_READ_BASE_ADDRESS FixedPcdGet64(PcdCntReadBase)
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#define CNT_CTL_BASE_ADDRESS FixedPcdGet64(PcdCntCTLBase)
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#define CNT_BASE0_ADDRESS FixedPcdGet64(PcdCntBase0)
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#define CNT_EL0_BASE0_ADDRESS FixedPcdGet64(PcdCntEL0Base0)
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#define SBSA_WATCHDOG_REFRESH_BASE FixedPcdGet64(PcdSbsaWatchDogRefreshBase)
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#define SBSA_WATCHDOG_CONTROL_BASE FixedPcdGet64(PcdSbsaWatchDogControlBase)
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#define SBSA_WAKEUP_GSIV FixedPcdGet64(PcdSbsaWakeUpGSIV)
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#define SBSA_WATCHDOG_GSIV FixedPcdGet64(PcdSbsaWatchDogGSIV)
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/*
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* Section 8.2.3 of Cortex-A15 r2p1 TRM
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*/
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#define CP15_TIMER_SEC_INTR 29
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#define CP15_TIMER_NS_INTR 30
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#define CP15_TIMER_VIRT_INTR 27
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#define CP15_TIMER_NSHYP_INTR 26
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/* SBSA Timers */
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#define PLATFORM_TIMER_COUNT 2
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#define PLATFORM_TIMER_OFFSET sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE)
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/*
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// GTDT Table timer flags.
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Bit 0: Timer interrupt Mode
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This bit indicates the mode of the timer interrupt
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1: Interrupt is Edge triggered
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0: Interrupt is Level triggered
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Timer Interrupt polarity
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This bit indicates the polarity of the timer interrupt
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1: Interrupt is Active low
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0: Interrupt is Active high
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Reserved 2 30 Reserved, must be zero.
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From A15 TRM:
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9.2 Generic Timer functional description
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...
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Each timer provides an active-LOW interrupt output that is an external pin to the SoC and is
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sent to the GIC as a Private Peripheral Interrupt (PPI). See Interrupt sources on page 8-4 for
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the ID and PPI allocation of the Timer interrupts.
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PPI6 Virtual Maintenance Interrupt.
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PPI5 Hypervisor timer event.
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PPI4 Virtual timer event.
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PPI3 nIRQ.
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PPI2 Non-secure physical timer event.
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PPI1 Secure physical timer event.
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PPI0-5 Active-LOW level-sensitive.
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PPI6 Active-HIGH level-sensitive.*/
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#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
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#define GTDT_TIMER_LEVEL_TRIGGERED 0
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#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
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#define GTDT_TIMER_ACTIVE_HIGH 0
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#define GTDT_TIMER_SECURE EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
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#define GTDT_TIMER_NON_SECURE 0
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#define GTDT_GTIMER_FLAGS (GTDT_TIMER_NON_SECURE | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_LEVEL_TRIGGERED)
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#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
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#define GTX_TIMER_LEVEL_TRIGGERED 0
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#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
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#define GTX_TIMER_ACTIVE_HIGH 0
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#define GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED)
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#define GTX_TIMER_SECURE EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
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#define GTX_TIMER_NON_SECURE 0
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#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
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#define GTX_TIMER_LOSE_CONTEXT 0
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#define GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE)
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#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
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#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0
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#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
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#define SBSA_WATCHDOG_ACTIVE_HIGH 0
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#define SBSA_WATCHDOG_SECURE EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
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#define SBSA_WATCHDOG_NON_SECURE 0
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#define SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED)
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#define AMD_SBSA_GTX { \
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EFI_ACPI_5_1_GTDT_GT_BLOCK, /* UINT8 Type */ \
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sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) + \
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sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), /* UINT16 Length */ \
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EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \
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CNT_CTL_BASE_ADDRESS, /* UINT64 CntCtlBase */ \
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1, /* UINT32 GTBlockTimerCount */ \
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sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) /* UINT32 GTBlockTimerOffset */ \
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}
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#define AMD_SBSA_GTX_TIMER { \
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0, /* UINT8 GTFrameNumber */ \
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{0, 0, 0}, /* UINT8 Reserved[3] */ \
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CNT_BASE0_ADDRESS, /* UINT64 CntBaseX */ \
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CNT_EL0_BASE0_ADDRESS, /* UINT64 CntEL0BaseX */ \
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SBSA_WAKEUP_GSIV, /* UINT32 GTxPhysicalTimerGSIV */ \
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GTX_TIMER_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
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0, /* UINT32 GTxVirtualTimerGSIV */ \
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GTX_TIMER_FLAGS, /* UINT32 GTxVirtualTimerFlags */ \
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GTX_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
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}
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#define AMD_SBSA_WATCHDOG { \
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EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG, /* UINT8 Type */ \
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sizeof (EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), /* UINT16 Length */ \
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EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \
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SBSA_WATCHDOG_REFRESH_BASE, /* UINT64 RefreshFramePhysicalAddress */ \
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SBSA_WATCHDOG_CONTROL_BASE, /* UINT64 WatchdogControlFramePhysicalAddress */ \
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SBSA_WATCHDOG_GSIV, /* UINT32 WatchdogTimerGSIV */ \
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SBSA_WATCHDOG_FLAGS /* UINT32 WatchdogTimerFlags */ \
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}
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typedef struct {
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EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
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EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE GTxBlock;
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EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE GTxTimer;
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EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE WatchDog;
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} AMD_ACPI_5_1_ARM_GTDT_STRUCTURE;
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STATIC AMD_ACPI_5_1_ARM_GTDT_STRUCTURE AcpiGtdt = {
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{
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AMD_ACPI_HEADER(EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
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AMD_ACPI_5_1_ARM_GTDT_STRUCTURE,
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EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION),
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CNT_CONTROL_BASE_ADDRESS, // UINT64 PhysicalAddress
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0, // UINT32 Reserved
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CP15_TIMER_SEC_INTR, // UINT32 SecureEL1TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 SecureEL1TimerFlags
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CP15_TIMER_NS_INTR, // UINT32 NonSecureEL1TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL1TimerFlags
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CP15_TIMER_VIRT_INTR, // UINT32 VirtualTimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
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CP15_TIMER_NSHYP_INTR, // UINT32 NonSecureEL2TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL2TimerFlags
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CNT_READ_BASE_ADDRESS, // UINT64 CntReadBaseAddress
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PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount
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PLATFORM_TIMER_OFFSET // UINT32 PlatformTimerOffset
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},
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AMD_SBSA_GTX,
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AMD_SBSA_GTX_TIMER,
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AMD_SBSA_WATCHDOG,
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};
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#pragma pack(pop)
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VOID* CONST ReferenceAcpiTable = &AcpiGtdt;
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