/** @file
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Differentiated System Description Table Fields (DSDT)
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Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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/**
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Derived from:
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ArmPlatformPkg/ArmJunoPkg/AcpiTables/Dsdt.asl
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**/
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#define NUM_CORES FixedPcdGet32 (PcdCoreCount)
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DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3)
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{
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Scope (_SB)
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{
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Device (CPU0)
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{
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Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
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Name (_UID, 0x000) // _UID: Unique ID
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}
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#if (NUM_CORES > 1)
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Device (CPU1)
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{
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Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
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Name (_UID, 0x001) // _UID: Unique ID
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}
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#endif
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#if (NUM_CORES > 2)
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Device (CPU2)
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{
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Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
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Name (_UID, 0x100) // _UID: Unique ID
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}
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#endif
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#if (NUM_CORES > 3)
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Device (CPU3)
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{
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Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
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Name (_UID, 0x101) // _UID: Unique ID
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}
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#endif
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#if (NUM_CORES > 4)
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Device (CPU4)
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{
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Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
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Name (_UID, 0x200) // _UID: Unique ID
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}
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#endif
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#if (NUM_CORES > 5)
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Device (CPU5)
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{
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Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
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Name (_UID, 0x201) // _UID: Unique ID
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}
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#endif
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#if (NUM_CORES > 6)
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Device (CPU6)
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{
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Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
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Name (_UID, 0x300) // _UID: Unique ID
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}
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#endif
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#if (NUM_CORES > 7)
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Device (CPU7)
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{
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Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
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Name (_UID, 0x301) // _UID: Unique ID
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}
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#endif
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Device (AHC0)
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{
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Name (_HID, "AMDI0600") // _HID: Hardware ID
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Name (_UID, 0x00) // _UID: Unique ID
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Name (_CLS, Package (0x03) // _CLS: Class Code
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{
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0x01,
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0x06,
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0x01
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})
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE0300000, // Address Base (MMIO)
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0x00010000, // Address Length
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)
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Memory32Fixed (ReadWrite,
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0xE0000078, // Address Base (SGPIO)
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0x00000001, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000183, }
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})
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}
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Device (SPI0)
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{
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Name (_HID, "AMDI0500") // _HID: Hardware ID
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Name (_UID, 0x00) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE1020000, // Address Base
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0x00001000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000016A, }
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})
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}
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Device (SPI1)
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{
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Name (_HID, "AMDI0500") // _HID: Hardware ID
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Name (_UID, 0x01) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE1030000, // Address Base
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0x00001000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000169, }
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})
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Device(SDC0)
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{
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Name(_HID, "AMDI0501") // SD Card/MMC slot
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Name(_CRS, ResourceTemplate()
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{
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SPISerialBus(1, // DeviceSelection
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PolarityLow, // DeviceSelectionPolarity
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FourWireMode, // WireMode
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8, // DataBitLength
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ControllerInitiated, // SlaveMode
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20000000, // ConnectionSpeed
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ClockPolarityLow, // ClockPolarity
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ClockPhaseFirst, // ClockPhase
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"\\SB.SPI1", // ResourceSource
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0, // ResourceSourceIndex
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ResourceConsumer, // ResourceUsage
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) // SPISerialBus()
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// SD Card “Detect” signal
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GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullDown, , "\\_SB.GIO1") {6}
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}) // ResourceTemplate()
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} // Device()
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}
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Device (COM1)
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{
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Name (_HID, "AMDI0511") // _HID: Hardware ID
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Name (_CID, "ARMH0011") // _CID: Compatible ID
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Name (_ADR, 0xE1010000) // _ADR: Address
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE1010000, // Address Base
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0x00001000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000168, }
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})
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}
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Device (GIO0)
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{
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Name (_HID, "AMDI0400") // _HID: Hardware ID
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Name (_CID, "ARMH0061") // _CID: Compatible ID
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Name (_UID, 0x00) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE0080000, // Address Base
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0x00001000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000189, }
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})
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}
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Device (GIO1)
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{
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Name (_HID, "AMDI0400") // _HID: Hardware ID
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Name (_CID, "ARMH0061") // _CID: Compatible ID
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Name (_UID, 0x01) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE1050000, // Address Base
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0x00001000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000186, }
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})
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}
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Device (I2C0)
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{
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Name (_HID, "AMDI0510") // _HID: Hardware ID
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Name (_UID, 0x00) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE1000000, // Address Base
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0x00001000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000185, }
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})
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Method (SSCN, 0, NotSerialized)
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{
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Return (Package (0x03)
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{
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0x0430,
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0x04E1,
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0x00
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})
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}
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Method (FMCN, 0, NotSerialized)
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{
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Return (Package (0x03)
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{
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0x00DE,
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0x018F,
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0x00
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})
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}
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}
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Device (I2C1)
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{
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Name (_HID, "AMDI0510") // _HID: Hardware ID
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Name (_UID, 0x01) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE0050000, // Address Base
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0x00001000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000174, }
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})
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Method (SSCN, 0, NotSerialized)
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{
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Return (Package (0x03)
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{
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0x0430,
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0x04E1,
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0x00
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})
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}
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Method (FMCN, 0, NotSerialized)
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{
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Return (Package (0x03)
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{
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0x00DE,
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0x018F,
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0x00
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})
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}
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}
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Device (CCP0)
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{
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Name (_HID, "AMDI0C00") // _HID: Hardware ID
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE0100000, // Address Base
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0x00010000, // Address Length
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)
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000023, }
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})
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Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
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{
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ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package ()
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{
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Package (0x02) {"amd,zlib-support", 1}
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}
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})
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}
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//
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// PCIe Root Bus
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//
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Device (PCI0)
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{
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Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
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Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
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Name (_SEG, 0x00) // _SEG: PCI Segment
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Name (_BBN, 0x00) // _BBN: BIOS Bus Number
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Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
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Name (_PRT, Package () // _PRT: PCI Routing Table
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{
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// INTA of the bridge device itself
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Package () { 0x2FFFF, 0x0, 0x0, 0x140 }
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})
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Device (EXP1)
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{
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Name (_ADR, 0x20001) // _ADR: Address
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Name (_PRT, Package () // _PRT: PCI Routing Table
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{
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Package () { 0xFFFF, 0x0, 0x0, 0x140 },
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Package () { 0xFFFF, 0x1, 0x0, 0x141 },
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Package () { 0xFFFF, 0x2, 0x0, 0x142 },
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Package () { 0xFFFF, 0x3, 0x0, 0x143 }
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}) // _PRT
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}
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Device (EXP2)
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{
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Name (_ADR, 0x20002) // _ADR: Address
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Name (_PRT, Package () // _PRT: PCI Routing Table
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{
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Package () { 0xFFFF, 0x0, 0x0, 0x144 },
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Package () { 0xFFFF, 0x1, 0x0, 0x145 },
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Package () { 0xFFFF, 0x2, 0x0, 0x146 },
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Package () { 0xFFFF, 0x3, 0x0, 0x147 }
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}) // _PRT
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}
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Device (EXP3)
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{
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Name (_ADR, 0x20003) // _ADR: Address
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Name (_PRT, Package () // _PRT: PCI Routing Table
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{
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Package () { 0xFFFF, 0x0, 0x0, 0x148 },
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Package () { 0xFFFF, 0x1, 0x0, 0x149 },
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Package () { 0xFFFF, 0x2, 0x0, 0x14A },
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Package () { 0xFFFF, 0x3, 0x0, 0x14B }
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}) // _PRT
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}
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Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
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{
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Name (RBUF, ResourceTemplate ()
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{
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, // Granularity
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0x0000, // Range Minimum
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0x007F, // Range Maximum
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0x0000, // Translation Offset
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0x0080, // Length
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)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x00000000, // Granularity
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0x40000000, // Range Minimum
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0xBFFFFFFF, // Range Maximum
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0x00000000, // Translation Offset
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0x80000000 // Length
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)
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QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x0000000000000000, // Granularity
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0x0000000100000000, // Range Minimum
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0x0000007FFFFFFFFF, // Range Maximum
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0x0000000000000000, // Translation Offset
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0x0000007F00000000 // Length
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)
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DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x00000000, // Granularity
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0x00000000, // Range Minimum
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0x0000FFFF, // Range Maximum
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0xEFFF0000, // Translation Address
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0x00010000, // Length
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,
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,
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,
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TypeTranslation
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)
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})
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Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
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} // Method(_CRS)
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Device (RES0)
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{
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Name (_HID, "PNP0C02")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0xF0000000, 0x8000000)
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})
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}
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Name (SUPP, 0x00)
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Name (CTRL, 0x00)
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Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
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{
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CreateDWordField (Arg3, 0x00, CDW1)
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If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
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{
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CreateDWordField (Arg3, 0x04, CDW2)
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CreateDWordField (Arg3, 0x08, CDW3)
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Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */
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Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */
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If (LNotEqual (And (SUPP, 0x16), 0x16))
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{
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And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */
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}
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And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */
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If (LNotEqual (Arg1, One))
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{
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Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
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}
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If (LNotEqual (CDW3, CTRL))
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{
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Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
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}
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Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */
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Return (Arg3)
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}
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Else
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{
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Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
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Return (Arg3)
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}
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} // Method(_OSC)
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//
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// Device-Specific Methods
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//
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Method(_DSM, 0x4, NotSerialized) {
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If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
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switch (ToInteger(Arg2)) {
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//
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// Function 0: Return supported functions
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//
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case(0) {
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Return (Buffer() {0x21})
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}
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//
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// Function 5: Return Ignore PCI Boot Configuration
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//
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case(5) {
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Return (0)
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}
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//
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// Not supported
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//
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default {
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}
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}
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}
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Return (Buffer(){0})
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} // Method(_DSM)
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}
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}
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}
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