/**
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*
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* Copyright (C) 2021, Semihalf.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Uefi.h>
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#include <Library/ArmadaBoardDescLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/MvGpioLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include "BoardDescriptionLib.h"
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STATIC
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VOID
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ConfigureIoWindow (
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UINT64 WinBaseAddress,
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UINT64 WinSize,
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UINTN WinId,
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UINT32 WinTargetId
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)
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{
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UINT32 AddressHigh;
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UINT32 AddressLow;
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UINT64 MaxAddress;
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/* Disable IO window. */
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MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), 0);
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/* Calculate the end address. */
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MaxAddress = (WinBaseAddress + WinSize - 1);
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AddressLow = (UINT32)((WinBaseAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WIN_ADDRESS_MASK);
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AddressLow |= IO_WIN_ENABLE_BIT;
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AddressHigh = (UINT32)((MaxAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WIN_ADDRESS_MASK);
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/* Write start address and end address for IO window. */
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MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), AddressLow);
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MmioWrite32 (IO_WIN_AHR_OFFSET(WinId), AddressHigh);
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/* Write window target. */
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MmioWrite32 (IO_WIN_CR_OFFSET(WinId), WinTargetId);
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}
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//
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// General purpose routine for per-board initalization
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//
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EFI_STATUS
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ArmadaBoardInit (
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VOID
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)
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{
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/*
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* Due to lack of sufficient number of IO windows registers,
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* the CP1/CP2 PCIE configuration must be performed after the
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* early firmware stages. Replace the MCI 0/1 indirect
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* windows, which are no longer needed.
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*/
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ConfigureIoWindow (
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CP1_PCIE_WIN64_BASE,
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CP1_PCIE_WIN64_SIZE,
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CP1_PCIE_WIN64_ID,
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MCI0_TARGET_ID
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);
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ConfigureIoWindow (
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CP2_PCIE_WIN64_BASE,
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CP2_PCIE_WIN64_SIZE,
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CP2_PCIE_WIN64_ID,
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MCI1_TARGET_ID
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);
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/* Enable FAN */
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MmioAnd32 (CP0_GPIO1_DATA_OUT_REG, ~CP0_GPIO1_PIN_MASK);
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MmioAnd32 (CP0_GPIO1_OUT_EN_REG, ~CP0_GPIO1_PIN_MASK);
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return EFI_SUCCESS;
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}
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//
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// GPIO Expander
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//
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EFI_STATUS
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EFIAPI
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ArmadaBoardGpioExpanderGet (
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IN OUT MV_GPIO_EXPANDER **GpioExpanders,
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IN OUT UINTN *GpioExpanderCount
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)
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{
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/* No GPIO expanders on board */
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*GpioExpanders = NULL;
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*GpioExpanderCount = 0;
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return EFI_SUCCESS;
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}
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//
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// PCIE
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//
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STATIC
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MV_PCIE_CONTROLLER mPcieController[] = {
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{ /* CP0 PCIE0 @0xF2600000 */
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.PcieDbiAddress = 0xF2600000,
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.ConfigSpaceAddress = 0x800000000,
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.HaveResetGpio = FALSE,
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.PcieResetGpio = { 0 },
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.PcieBusMin = 0,
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.PcieBusMax = 0xFE,
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.PcieIoTranslation = 0x80FF00000,
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.PcieIoWinBase = 0x0,
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.PcieIoWinSize = 0x10000,
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.PcieMmio32Translation = 0,
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.PcieMmio32WinBase = 0xC0000000,
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.PcieMmio32WinSize = 0x20000000,
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.PcieMmio64Translation = 0,
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.PcieMmio64WinBase = 0x810000000,
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.PcieMmio64WinSize = 0x80000000,
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},
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{ /* CP1 PCIE0 @0xF4600000 */
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.PcieDbiAddress = 0xF4600000,
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.ConfigSpaceAddress = 0xE2000000,
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.HaveResetGpio = FALSE,
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.PcieResetGpio = { 0 },
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.PcieBusMin = 0,
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.PcieBusMax = 0xE,
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.PcieIoTranslation = 0xE2F00000,
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.PcieIoWinBase = 0x0,
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.PcieIoWinSize = 0x10000,
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.PcieMmio32Translation = 0,
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.PcieMmio32WinBase = 0xE3000000,
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.PcieMmio32WinSize = 0x1000000,
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.PcieMmio64Translation = 0,
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.PcieMmio64WinBase = 0x890000000,
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.PcieMmio64WinSize = 0x10000000,
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},
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{ /* CP1 PCIE1 @0xF4620000 */
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.PcieDbiAddress = 0xF4620000,
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.ConfigSpaceAddress = 0xE4000000,
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.HaveResetGpio = FALSE,
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.PcieResetGpio = { 0 },
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.PcieBusMin = 0,
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.PcieBusMax = 0xE,
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.PcieIoTranslation = 0xE4F00000,
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.PcieIoWinBase = 0x0,
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.PcieIoWinSize = 0x10000,
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.PcieMmio32Translation = 0,
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.PcieMmio32WinBase = 0xE5000000,
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.PcieMmio32WinSize = 0x1000000,
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.PcieMmio64Translation = 0,
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.PcieMmio64WinBase = 0x8A0000000,
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.PcieMmio64WinSize = 0x10000000,
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},
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{ /* CP1 PCIE2 @0xF4640000 */
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.PcieDbiAddress = 0xF4640000,
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.ConfigSpaceAddress = 0xE6000000,
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.HaveResetGpio = FALSE,
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.PcieResetGpio = { 0 },
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.PcieBusMin = 0,
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.PcieBusMax = 0xE,
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.PcieIoTranslation = 0xE6F00000,
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.PcieIoWinBase = 0x0,
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.PcieIoWinSize = 0x10000,
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.PcieMmio32Translation = 0,
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.PcieMmio32WinBase = 0xE7000000,
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.PcieMmio32WinSize = 0x1000000,
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.PcieMmio64Translation = 0,
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.PcieMmio64WinBase = 0x8B0000000,
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.PcieMmio64WinSize = 0x10000000,
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},
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{ /* CP2 PCIE0 @0xF6600000 */
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.PcieDbiAddress = 0xF6600000,
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.ConfigSpaceAddress = 0xE9000000,
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.HaveResetGpio = FALSE,
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.PcieResetGpio = { 0 },
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.PcieBusMin = 0,
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.PcieBusMax = 0xE,
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.PcieIoTranslation = 0xE9F00000,
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.PcieIoWinBase = 0x0,
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.PcieIoWinSize = 0x10000,
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.PcieMmio32Translation = 0,
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.PcieMmio32WinBase = 0xEA000000,
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.PcieMmio32WinSize = 0x1000000,
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.PcieMmio64Translation = 0,
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.PcieMmio64WinBase = 0x8C0000000,
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.PcieMmio64WinSize = 0x10000000,
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},
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{ /* CP2 PCIE1 @0xF6620000 */
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.PcieDbiAddress = 0xF6620000,
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.ConfigSpaceAddress = 0xEB000000,
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.HaveResetGpio = FALSE,
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.PcieResetGpio = { 0 },
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.PcieBusMin = 0,
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.PcieBusMax = 0xE,
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.PcieIoTranslation = 0xEBF00000,
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.PcieIoWinBase = 0x0,
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.PcieIoWinSize = 0x10000,
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.PcieMmio32Translation = 0,
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.PcieMmio32WinBase = 0xEC000000,
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.PcieMmio32WinSize = 0x1000000,
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.PcieMmio64Translation = 0,
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.PcieMmio64WinBase = 0x8D0000000,
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.PcieMmio64WinSize = 0x10000000,
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},
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{ /* CP2 PCIE2 @0xF6640000 */
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.PcieDbiAddress = 0xF6640000,
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.ConfigSpaceAddress = 0xED000000,
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.HaveResetGpio = FALSE,
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.PcieResetGpio = { 0 },
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.PcieBusMin = 0,
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.PcieBusMax = 0xE,
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.PcieIoTranslation = 0xEDF00000,
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.PcieIoWinBase = 0x0,
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.PcieIoWinSize = 0x10000,
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.PcieMmio32Translation = 0,
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.PcieMmio32WinBase = 0xEE000000,
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.PcieMmio32WinSize = 0x1000000,
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.PcieMmio64Translation = 0,
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.PcieMmio64WinBase = 0x8E0000000,
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.PcieMmio64WinSize = 0x10000000,
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},
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};
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/**
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Return the number and description of PCIE controllers used on the platform.
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@param[in out] **PcieControllers Array containing PCIE controllers'
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description.
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@param[in out] *PcieControllerCount Amount of used PCIE controllers.
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@retval EFI_SUCCESS The data were obtained successfully.
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@retval other Return error status.
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**/
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EFI_STATUS
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EFIAPI
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ArmadaBoardPcieControllerGet (
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IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,
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IN OUT UINTN *PcieControllerCount
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)
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{
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*PcieControllers = mPcieController;
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*PcieControllerCount = ARRAY_SIZE (mPcieController);
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return EFI_SUCCESS;
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}
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//
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// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib
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//
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STATIC
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MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = {
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{ /* eMMC 0xF06E0000 */
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0, /* SOC will be filled by MvBoardDescDxe */
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0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
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TRUE, /* Xenon1v8Enabled */
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/*
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* Force 4-bit bus width - work-around for non
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* functional HS400 mode.
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*/
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FALSE, /* Xenon8BitBusEnabled */
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FALSE, /* XenonSlowModeEnabled */
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0x40, /* XenonTuningStepDivisor */
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EmbeddedSlot /* SlotType */
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},
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{ /* SD/MMC 0xF2780000 */
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0, /* SOC will be filled by MvBoardDescDxe */
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0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
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FALSE, /* Xenon1v8Enabled */
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FALSE, /* Xenon8BitBusEnabled */
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FALSE, /* XenonSlowModeEnabled */
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0x19, /* XenonTuningStepDivisor */
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EmbeddedSlot /* SlotType */
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},
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};
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EFI_STATUS
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EFIAPI
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ArmadaBoardDescSdMmcGet (
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OUT UINTN *SdMmcDevCount,
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OUT MV_BOARD_SDMMC_DESC **SdMmcDesc
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)
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{
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*SdMmcDesc = mSdMmcDescTemplate;
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*SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate);
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return EFI_SUCCESS;
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}
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