#Copyright (C) 2017 Marvell International Ltd.
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#
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#SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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################################################################################
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#
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# Defines Section - statements that will be processed to create a Makefile.
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#
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################################################################################
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[Defines]
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PLATFORM_NAME = Armada80x0McBin
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PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
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PLATFORM_VERSION = 0.1
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DSC_SPECIFICATION = 0x0001001A
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OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
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SUPPORTED_ARCHITECTURES = AARCH64|ARM
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BUILD_TARGETS = DEBUG|RELEASE|NOOPT
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SKUID_IDENTIFIER = DEFAULT
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FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
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BOARD_DXE_FV_COMPONENTS = Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
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CAPSULE_ENABLE = TRUE
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#
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# Network definition
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#
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DEFINE NETWORK_IP6_ENABLE = FALSE
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DEFINE NETWORK_TLS_ENABLE = FALSE
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DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
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DEFINE NETWORK_ISCSI_ENABLE = FALSE
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!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
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!include MdePkg/MdeLibs.dsc.inc
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[Components.common]
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Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
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[Components.AARCH64]
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Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
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[LibraryClasses.common]
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ArmadaBoardDescLib|Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf
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NonDiscoverableInitLib|Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
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################################################################################
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#
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# Pcd Section - list of all EDK II PCD Entries defined by this Platform
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#
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################################################################################
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[PcdsFixedAtBuild.common]
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#Platform description
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gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
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gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 MacchiatoBin"
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gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.3"
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#MPP
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gMarvellTokenSpaceGuid.PcdMppChipCount|3
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# APN806-A0 MPP SET
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gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
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gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
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gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
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gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
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gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
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# CP110 MPP SET - master
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gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
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gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
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gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
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gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
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gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
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gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
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gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
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gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
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gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
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gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
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# CP110 MPP SET - slave
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gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
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gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
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gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
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gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
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gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
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gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
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gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
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gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
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gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
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gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
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#SPI
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gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
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gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
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gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
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gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
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gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
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#ComPhy
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gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
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# ComPhy0
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# 0: PCIE0 5 Gbps
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# 1: PCIE0 5 Gbps
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# 2: PCIE0 5 Gbps
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# 3: PCIE0 5 Gbps
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# 4: SFI 10.31 Gbps
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# 5: SATA1 5 Gbps
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gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
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gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
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# ComPhy1
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# 0: SGMII1 1.25 Gbps
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# 1: SATA0 5 Gbps
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# 2: USB3_HOST0 5 Gbps
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# 3: SATA1 5 Gbps
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# 4: SFI 10.31 Gbps
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# 5: SGMII2 3.125 Gbps
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gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
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gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
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#UtmiPhy
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gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
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gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
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#MDIO
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gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
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#PHY
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gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
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gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
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gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
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gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
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#NET
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gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
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gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
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gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
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gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
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gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
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gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
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gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
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gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
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#PciEmulation
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gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
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gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
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gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
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#RTC
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gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000
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