/**@file
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Build up platform processor information.
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Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// The package level header files this module uses
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//
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#include <PiPei.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <SmbiosProcessorSpecificData.h>
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#include <ProcessorSpecificHobData.h>
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#include <SiFiveU5MCCoreplex.h>
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#include <Library/SiFiveU54.h>
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/**
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Build up processor-specific HOB for U5MC Coreplex
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@param UniqueId Unique ID of this U5MC Coreplex processor
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@return EFI_SUCCESS The PEIM initialized successfully.
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**/
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EFI_STATUS
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EFIAPI
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CreateU5MCCoreplexProcessorSpecificDataHob (
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IN UINTN UniqueId
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)
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{
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EFI_STATUS Status;
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UINT32 HartIdNumber;
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RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *GuidHobData;
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EFI_GUID *ParentCoreGuid;
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BOOLEAN MCSupport;
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DEBUG ((DEBUG_INFO, "Building U5 Coreplex processor information HOB\n"));
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HartIdNumber = 0;
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ParentCoreGuid = PcdGetPtr(PcdSiFiveU5MCCoreplexGuid);
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MCSupport = PcdGetBool (PcdE5MCSupported);
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if (MCSupport == TRUE) {
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Status = CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, FALSE, TRUE, &GuidHobData);
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if (EFI_ERROR (Status) && Status != EFI_UNSUPPORTED) {
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DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\n"));
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ASSERT (FALSE);
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} else {
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if (!EFI_ERROR (Status)) {
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DEBUG((DEBUG_INFO, "Support E5 Monitor core on U5 platform, HOB at address 0x%x\n", GuidHobData));
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}
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}
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HartIdNumber ++;
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}
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for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + (UINT32)MCSupport); HartIdNumber ++) {
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Status = CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId)), FALSE, &GuidHobData);
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if (EFI_ERROR (Status) && Status != EFI_UNSUPPORTED) {
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DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\n"));
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ASSERT (FALSE);
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} else {
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if (!EFI_ERROR (Status)) {
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DEBUG ((DEBUG_INFO, "Support U5 application core on U5 platform, HOB Data at address 0x%x\n", GuidHobData));
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}
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}
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}
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DEBUG ((DEBUG_INFO, "Support %d U5 application cores on U5 platform\n", HartIdNumber - (UINT32)MCSupport));
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if (HartIdNumber != FixedPcdGet32 (PcdHartCount)) {
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DEBUG ((DEBUG_ERROR, "Improper core settings...\n"));
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DEBUG ((DEBUG_ERROR, " PcdHartCount\n"));
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DEBUG ((DEBUG_ERROR, " PcdNumberofU5Cores\n"));
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DEBUG ((DEBUG_ERROR, " PcdE5MCSupported\n\n"));
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ASSERT (FALSE);
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}
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return Status;
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}
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/**
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Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
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this information and build SMBIOS Type4 and Type7 record.
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@param ProcessorUid Unique ID of physical processor which owns this core.
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@param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
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maintained in this structure is only valid before memory is discovered.
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Access to those pointers after memory is installed will cause unexpected issues.
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@return EFI_SUCCESS The SMBIOS Hobs were created successfully.
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**/
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EFI_STATUS
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EFIAPI
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CreateU5MCProcessorSmbiosDataHob (
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IN UINTN ProcessorUid,
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OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
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)
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{
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EFI_GUID *GuidPtr;
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RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;
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RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
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RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
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RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1CacheDataHobPtr;
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RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;
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RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
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DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
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if (SmbiosHobPtr == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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CreateU54SmbiosType7L1DataHob (ProcessorUid, &L1CacheDataHobPtr);
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CreateU54SmbiosType4DataHob (ProcessorUid, &ProcessorDataHobPtr);
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//
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// Build up SMBIOS type 7 L2 cache record.
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//
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ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
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L2CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
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L2CacheDataHob.ProcessorUid = ProcessorUid;
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L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
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L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
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RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \
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RISC_V_CACHE_CONFIGURATION_ENABLED | \
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RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
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L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
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L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
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L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
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L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
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L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
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L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
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L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
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L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
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GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
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L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
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if (L2CacheDataHobPtr == NULL) {
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DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
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ASSERT (FALSE);
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}
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ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
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SmbiosDataHob.Processor = ProcessorDataHobPtr;
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SmbiosDataHob.L1Cache = L1CacheDataHobPtr;
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SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
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SmbiosDataHob.L3Cache = NULL;
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GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
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SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
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if (SmbiosDataHobPtr == NULL) {
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DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));
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ASSERT (FALSE);
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}
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*SmbiosHobPtr = SmbiosDataHobPtr;
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DEBUG ((DEBUG_INFO, "%a: Exit\n", __FUNCTION__));
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return EFI_SUCCESS;
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}
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