/*
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*
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* Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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*/
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#include <libfdt.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/sifive-uart.h>
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#include <sbi_utils/sys/clint.h>
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#include <U5Clint.h>
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#define U500_HART_COUNT FixedPcdGet32(PcdHartCount)
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#define U500_BOOTABLE_HART_COUNT FixedPcdGet32(PcdBootableHartNumber)
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#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize)
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#define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId)
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#define U500_SYS_CLK FixedPcdGet32(PcdU5PlatformSystemClock)
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#define U500_PLIC_ADDR 0xc000000
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#define U500_PLIC_NUM_SOURCES 0x35
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#define U500_PLIC_NUM_PRIORITIES 7
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#define U500_UART_ADDR FixedPcdGet32(PcdU5UartBase)
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#define U500_UART_BAUDRATE 115200
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/* PRCI clock related macros */
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//TODO: Do we need a separate driver for this ?
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#define U500_PRCI_BASE_ADDR 0x10000000
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#define U500_PRCI_CLKMUXSTATUSREG 0x002C
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#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
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/* Full tlb flush always */
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#define U500_TLB_RANGE_FLUSH_LIMIT 0
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unsigned long log2roundup(unsigned long x);
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static struct plic_data plic = {
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.addr = U500_PLIC_ADDR,
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.num_src = U500_PLIC_NUM_SOURCES,
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};
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static struct clint_data clint = {
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.addr = CLINT_REG_BASE_ADDR,
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.first_hartid = 0,
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.hart_count = U500_HART_COUNT,
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.has_64bit_mmio = TRUE,
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};
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static void U500_modify_dt(void *fdt)
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{
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u32 i, size;
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int chosen_offset, err;
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int cpu_offset;
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char cpu_node[32] = "";
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const char *mmu_type;
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for (i = 0; i < U500_HART_COUNT; i++) {
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sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
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cpu_offset = fdt_path_offset(fdt, cpu_node);
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mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
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if (mmu_type && (!AsciiStrCmp(mmu_type, "riscv,sv39") ||
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!AsciiStrCmp(mmu_type,"riscv,sv48")))
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continue;
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else
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fdt_setprop_string(fdt, cpu_offset, "status", "masked");
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memset(cpu_node, 0, sizeof(cpu_node));
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}
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size = fdt_totalsize(fdt);
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err = fdt_open_into(fdt, fdt, size + 256);
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if (err < 0)
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sbi_printf("Device Tree can't be expanded to accmodate new node");
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chosen_offset = fdt_path_offset(fdt, "/chosen");
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fdt_setprop_string(fdt, chosen_offset, "stdout-path",
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"/soc/serial@10010000:115200");
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fdt_plic_fixup(fdt, "riscv,plic0");
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}
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static int U500_final_init(bool cold_boot)
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{
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void *fdt;
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struct sbi_scratch *ThisScratch;
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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U500_modify_dt(fdt);
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//
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// Set PMP of firmware regions to R and X. We will lock this in the end of PEI.
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// This region only protects SEC, PEI and Scratch buffer.
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//
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ThisScratch = sbi_scratch_thishart_ptr ();
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pmp_set(0, PMP_R | PMP_X | PMP_W, ThisScratch->fw_start, log2roundup (ThisScratch->fw_size));
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return 0;
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}
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static u32 U500_pmp_region_count(u32 hartid)
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{
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return 1;
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}
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static int U500_pmp_region_info(u32 hartid, u32 index,
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ulong *prot, ulong *addr, ulong *log2size)
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{
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int ret = 0;
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switch (index) {
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case 0:
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*prot = PMP_R | PMP_W | PMP_X;
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*addr = 0;
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*log2size = __riscv_xlen;
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break;
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default:
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ret = -1;
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break;
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};
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return ret;
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}
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static int U500_console_init(void)
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{
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unsigned long peri_in_freq;
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peri_in_freq = U500_SYS_CLK/2;
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return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRATE);
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}
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static int U500_irqchip_init(bool cold_boot)
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{
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int rc;
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u32 hartid = current_hartid();
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if (cold_boot) {
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rc = plic_cold_irqchip_init(&plic);
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if (rc)
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return rc;
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}
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return plic_warm_irqchip_init(&plic,
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(hartid) ? (2 * hartid - 1) : 0,
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(hartid) ? (2 * hartid) : -1);
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}
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static int U500_ipi_init(bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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rc = clint_cold_ipi_init(&clint);
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if (rc)
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return rc;
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}
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return clint_warm_ipi_init();
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}
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static u64 U500_get_tlbr_flush_limit(void)
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{
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return U500_TLB_RANGE_FLUSH_LIMIT;
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}
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static int U500_timer_init(bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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rc = clint_cold_timer_init(&clint, NULL);
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if (rc)
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return rc;
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}
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return clint_warm_timer_init();
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}
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/**
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* The U500 SoC has 4 HARTs, Boot HART ID is determined by
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* PcdBootHartId.
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*/
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static u32 u500_hart_index2id[U500_BOOTABLE_HART_COUNT] = {0, 1, 2, 3};
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static int U500_system_reset(u32 type)
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{
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/* For now nothing to do. */
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return 0;
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}
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const struct sbi_platform_operations platform_ops = {
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.pmp_region_count = U500_pmp_region_count,
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.pmp_region_info = U500_pmp_region_info,
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.final_init = U500_final_init,
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.console_putc = sifive_uart_putc,
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.console_getc = sifive_uart_getc,
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.console_init = U500_console_init,
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.irqchip_init = U500_irqchip_init,
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.ipi_send = clint_ipi_send,
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.ipi_clear = clint_ipi_clear,
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.ipi_init = U500_ipi_init,
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.get_tlbr_flush_limit = U500_get_tlbr_flush_limit,
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.timer_value = clint_timer_value,
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.timer_event_stop = clint_timer_event_stop,
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.timer_event_start = clint_timer_event_start,
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.timer_init = U500_timer_init,
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.system_reset = U500_system_reset
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
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.platform_version = SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI Platform version 1.0
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.name = "SiFive Freedom U500",
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.features = SBI_PLATFORM_DEFAULT_FEATURES,
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.hart_count = U500_BOOTABLE_HART_COUNT,
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.hart_index2id = u500_hart_index2id,
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.hart_stack_size = U500_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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