/** @file
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*
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* Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
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* Copyright (c) Microsoft Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include "RockchipSdhci.h"
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#include <Library/PcdLib.h>
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#include <Library/TimerLib.h>
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#define word32 *(volatile unsigned int *)(long)
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#define word16 *(volatile unsigned short *)(long)
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//#define GRF_BASE 0xFDC60000
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#define NS_CRU_BASE 0xFD7C0000
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#define CRU_CLKSEL_CON77 0x0434
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#define CRU_GPLL_CON1 0x1C4
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#define CRU_CPLL_CON1 0x1A4
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#define EMMC_CLOCK_BASE (NS_CRU_BASE + CRU_CLKSEL_CON77)
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#define EMMC_CLOCK_SEL(a) (((7 << 12) << 16) | (a << 12))
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#define EMMC_BASE PcdGet32 (PcdSdhciDxeBaseAddress)
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#define SDHCI_HOST_CTRL2 (EMMC_BASE + 0x3E)
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#define SDHCI_HOST_CTRL3 (EMMC_BASE + 0x508)
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#define SDHCI_EMMC_CTRL (EMMC_BASE + 0x52C)
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#define EMMC_DLL_CTRL (EMMC_BASE + 0x800)
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#define EMMC_DLL_RXCLK (EMMC_BASE + 0x804)
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#define EMMC_DLL_TXCLK (EMMC_BASE + 0x808)
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#define EMMC_DLL_STRBIN (EMMC_BASE + 0x80C)
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#define EMMC_DLL_CMDOUT (EMMC_BASE + 0x810)
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#define EMMC_DLL_STATUS0 (EMMC_BASE + 0x840)
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#define EMMC_DLL_STATUS1 (EMMC_BASE + 0x844)
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EFI_STATUS SdhciSetPHY(
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IN UINTN Clock
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)
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{
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UINT32 Ctrl2;
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UINT32 status, timeout, tmp;
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word32(SDHCI_EMMC_CTRL) |= (1 << 0); /* Host Controller is an eMMC card */
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if (Clock < 100000000) {
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word32(EMMC_DLL_CTRL) = 0;
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word32(EMMC_DLL_RXCLK) = 0; /* PIO mode need set bit 29*/
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word32(EMMC_DLL_TXCLK) = 0;
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word32(EMMC_DLL_STRBIN) = 0;
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word32(EMMC_DLL_CMDOUT) = 0;
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goto exit;
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}
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word32(EMMC_DLL_RXCLK) = 0;
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/*Reset DLL*/
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word32(EMMC_DLL_CTRL) = (0x1 << 1);
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MicroSecondDelay(5);
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word32(EMMC_DLL_CTRL) = 0;
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/*Init DLL*/
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word32(EMMC_DLL_CTRL) = (5 << 16) | (2 << 8) | 0x1;
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/* Wait max 10 ms */
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timeout = 10000;
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while (1) {
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status = word32(EMMC_DLL_STATUS0);
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tmp = (status >> 8) & 0x3;
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if (0x1 == tmp) /*check dll lock*/
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break;
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if (timeout-- > 0)
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MicroSecondDelay(1);
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else {
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DEBUG ((DEBUG_ERROR, "%a timeout status:%x\n", __FUNCTION__, status));
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return EFI_TIMEOUT;
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}
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}
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Ctrl2 = word16(SDHCI_HOST_CTRL2) & 0x0007; /* Get Bus Speed Mode*/
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if (Clock >= 200000000 && Ctrl2 == 0x7) { /*check is HS400 mode*/
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word32(SDHCI_EMMC_CTRL) |= (1 << 8); /* CMD line is sampled using data strobe for HS400 mode */
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word32(EMMC_DLL_RXCLK) = (1 << 27);
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word32(EMMC_DLL_TXCLK) = (1 << 29) | (1 << 27) | (1 << 24) | 0x8;
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word32(EMMC_DLL_STRBIN) = (1 << 27) | (1 << 24) | 0x4;
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}
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else { /*config for HS200 mode*/
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word32(EMMC_DLL_RXCLK) = (1 << 29) | (1 << 27);
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word32(EMMC_DLL_TXCLK) = (1 << 27) | (1 << 24) | 0x1;
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word32(EMMC_DLL_STRBIN) = 0; //max is 16
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}
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exit:
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//DEBUG ((DEBUG_ERROR, "EMMC_DLL_CTRL :0x%x\n", word32(EMMC_DLL_CTRL)));
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//DEBUG ((DEBUG_ERROR, "EMMC_DLL_RXCLK:0x%x\n", word32(EMMC_DLL_RXCLK)));
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//DEBUG ((DEBUG_ERROR, "EMMC_DLL_TXCLK:0x%x\n", word32(EMMC_DLL_TXCLK)));
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//DEBUG ((DEBUG_ERROR, "EMMC_DLL_STRBIN:0x%x\n", word32(EMMC_DLL_STRBIN)));
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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SdhciGetClockRate(
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IN UINTN TargetFreq,
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OUT UINTN *BaseFreq
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)
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{
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UINT32 CClkEmmcSel, Div;
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if (TargetFreq == 0 || BaseFreq == NULL)
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return -1;
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//word32(NS_CRU_BASE + CRU_GPLL_CON1) = 0x70002 << 6; //GPLL:600MHz
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//word32(NS_CRU_BASE + CRU_CPLL_CON1) = 0x70002 << 6; //CPLL:750MHZ
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/*GPLL:1184MHz, CPLL:750MHZ
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2'b00: clk_gpll_mux
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2'b01: clk_cpll_mux
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2'b10: xin_osc0_func*/
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if (TargetFreq >= 200000000) {
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CClkEmmcSel = 0;
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Div = 6;
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} else if (TargetFreq >= 150000000) {
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CClkEmmcSel = 0;
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Div = 8;
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} else if (TargetFreq >= 100000000) {
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CClkEmmcSel = 0;
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Div = 12;
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} else if (TargetFreq >= 50000000) {
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CClkEmmcSel = 0;
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Div = 24;
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} else if (TargetFreq >= 24000000) {
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CClkEmmcSel = 2;
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Div = 1;
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} else { /* 375KHZ*/
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CClkEmmcSel = 2;
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Div = 64;
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}
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DEBUG((DEBUG_ERROR, "+++++SetEmmcClk: %d, %d, %d\n", TargetFreq, CClkEmmcSel, Div));
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*BaseFreq = TargetFreq;
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MmioWrite32(EMMC_CLOCK_BASE, ((( 0x3 << 14 )|( 0x3F << 8 )) << 16 ) |
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( CClkEmmcSel << 14 ) |
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(( Div - 1 ) << 8));
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//DEBUG ((DEBUG_ERROR, "CRU_0X434: 0x%x\n", word32(NS_CRU_BASE + 0x0434)));
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//DEBUG ((DEBUG_ERROR, "CRU_0X438: 0x%x\n", word32(NS_CRU_BASE + 0x0438)));
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//DEBUG ((DEBUG_ERROR, "GPLL_CON1: 0x%x\n", word32(NS_CRU_BASE + CRU_GPLL_CON1)));
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//DEBUG ((DEBUG_ERROR, "CPLL_CON1: 0x%x\n", word32(NS_CRU_BASE + CRU_CPLL_CON1)));
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SdhciSetPHY(TargetFreq);
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return EFI_SUCCESS;
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}
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