/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include "Include/Library/CruLib.h"
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#include <Library/DebugLib.h>
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/** @addtogroup RK_HAL_Driver
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* @{
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*/
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/** @addtogroup CRU
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* @{
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*/
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/** @defgroup CRU_Private_Definition Private Definition
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* @{
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*/
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/********************* Private MACRO Definition ******************************/
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/********************* Private Structure Definition **************************/
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static struct PLL_CONFIG PLL_TABLE[] = {
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/* _mhz, _refDiv, _fbDiv, _postdDv1, _postDiv2, _dsmpd, _frac */
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RK3588_PLL_RATE(1680000000, 2, 280, 1, 0),
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RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
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RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),
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RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
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RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
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RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
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RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
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RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
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RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
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{ /* sentinel */ },
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};
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static struct PLL_SETUP LPLL = {
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.conOffset0 = &(DSUCRU->LPLL_CON[0]),
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.conOffset1 = &(DSUCRU->LPLL_CON[1]),
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.conOffset2 = &(DSUCRU->LPLL_CON[2]),
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.conOffset3 = &(DSUCRU->LPLL_CON[3]),
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.conOffset6 = &(DSUCRU->LPLL_CON[6]),
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.modeOffset = &(DSUCRU->MODE_CON00),
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.modeShift = 0,
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.lockShift = 15,
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.modeMask = 0x3,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP B0PLL = {
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.conOffset0 = &(BIGCORE0CRU->B0PLL_CON[0]),
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.conOffset1 = &(BIGCORE0CRU->B0PLL_CON[1]),
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.conOffset2 = &(BIGCORE0CRU->B0PLL_CON[2]),
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.conOffset3 = &(BIGCORE0CRU->B0PLL_CON[3]),
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.conOffset6 = &(BIGCORE0CRU->B0PLL_CON[6]),
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.modeOffset = &(BIGCORE0CRU->MODE_CON00),
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.modeShift = 0,
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.lockShift = 15,
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.modeMask = 0x3,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP B1PLL = {
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.conOffset0 = &(BIGCORE1CRU->B1PLL_CON[0]),
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.conOffset1 = &(BIGCORE1CRU->B1PLL_CON[1]),
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.conOffset2 = &(BIGCORE1CRU->B1PLL_CON[2]),
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.conOffset3 = &(BIGCORE1CRU->B1PLL_CON[3]),
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.conOffset6 = &(BIGCORE1CRU->B1PLL_CON[6]),
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.modeOffset = &(BIGCORE1CRU->MODE_CON00),
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.modeShift = 0,
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.lockShift = 15,
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.modeMask = 0x3,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP CPLL = {
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.conOffset0 = &(CRU->CPLL_CON[0]),
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.conOffset1 = &(CRU->CPLL_CON[1]),
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.conOffset2 = &(CRU->CPLL_CON[2]),
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.conOffset3 = &(CRU->CPLL_CON[3]),
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.conOffset6 = &(CRU->CPLL_CON[6]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 8,
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.lockShift = 15,
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.modeMask = 0x3 << 8,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP GPLL = {
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.conOffset0 = &(CRU->GPLL_CON[0]),
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.conOffset1 = &(CRU->GPLL_CON[1]),
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.conOffset2 = &(CRU->GPLL_CON[2]),
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.conOffset3 = &(CRU->GPLL_CON[3]),
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.conOffset6 = &(CRU->GPLL_CON[6]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 2,
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.lockShift = 15,
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.modeMask = 0x3 << 2,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP NPLL = {
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.conOffset0 = &(CRU->NPLL_CON[0]),
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.conOffset1 = &(CRU->NPLL_CON[1]),
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.conOffset2 = &(CRU->NPLL_CON[2]),
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.conOffset3 = &(CRU->NPLL_CON[3]),
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.conOffset6 = &(CRU->NPLL_CON[6]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 0,
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.lockShift = 15,
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.modeMask = 0x3 << 0,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP V0PLL = {
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.conOffset0 = &(CRU->V0PLL_CON[0]),
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.conOffset1 = &(CRU->V0PLL_CON[1]),
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.conOffset2 = &(CRU->V0PLL_CON[2]),
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.conOffset3 = &(CRU->V0PLL_CON[3]),
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.conOffset6 = &(CRU->V0PLL_CON[6]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 4,
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.lockShift = 15,
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.modeMask = 0x3 << 4,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP AUPLL = {
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.conOffset0 = &(CRU->AUPLL_CON[0]),
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.conOffset1 = &(CRU->AUPLL_CON[1]),
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.conOffset2 = &(CRU->AUPLL_CON[2]),
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.conOffset3 = &(CRU->AUPLL_CON[3]),
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.conOffset6 = &(CRU->AUPLL_CON[6]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 6,
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.lockShift = 15,
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.modeMask = 0x3 << 6,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP PPLL = {
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.conOffset0 = &(PHPTOPCRU->PPLL_CON[0]),
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.conOffset1 = &(PHPTOPCRU->PPLL_CON[1]),
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.conOffset2 = &(PHPTOPCRU->PPLL_CON[2]),
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.conOffset3 = &(PHPTOPCRU->PPLL_CON[3]),
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.conOffset6 = &(PHPTOPCRU->PPLL_CON[6]),
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.lockShift = 15,
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.rateTable = PLL_TABLE,
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};
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/********************* Private Variable Definition ***************************/
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static uint32_t s_lpllFreq;
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static uint32_t s_cpllFreq = 1500 * 1000 * 1000;;
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static uint32_t s_gpllFreq = 1188 * 1000 * 1000;
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static uint32_t s_npllFreq;
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static uint32_t s_v0pllFreq;
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static uint32_t s_ppllFreq;
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static uint32_t s_aupllFreq;
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/********************* Private Function Definition ***************************/
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/** @} */
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/********************* Public Function Definition ****************************/
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/**
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* @brief Get clk freq.
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* @param clockName: CLOCK_Name id.
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* @return rate.
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* @attention these APIs allow direct use in the HAL layer.
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*/
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uint32_t
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EFIAPI
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HAL_CRU_ClkGetFreq(eCLOCK_Name clockName)
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{
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uint32_t clkMux = CLK_GET_MUX(clockName);
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uint32_t clkDiv = CLK_GET_DIV(clockName);
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uint32_t pRate = 0, freq;
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if (!s_cpllFreq) {
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s_cpllFreq = HAL_CRU_GetPllV1Freq(&CPLL);
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}
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switch (clockName) {
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case PLL_LPLL:
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freq = HAL_CRU_GetPllV1Freq(&LPLL);
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s_lpllFreq = freq;
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return freq;
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case PLL_B0PLL:
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freq = HAL_CRU_GetPllV1Freq(&B0PLL);
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return freq;
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case PLL_B1PLL:
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freq = HAL_CRU_GetPllV1Freq(&B1PLL);
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return freq;
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case PLL_CPLL:
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freq = HAL_CRU_GetPllV1Freq(&CPLL);
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s_cpllFreq = freq;
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return freq;
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case PLL_NPLL:
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freq = HAL_CRU_GetPllV1Freq(&NPLL);
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s_npllFreq = freq;
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return freq;
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case PLL_V0PLL:
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freq = HAL_CRU_GetPllV1Freq(&V0PLL);
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s_v0pllFreq = freq;
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return freq;
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case PLL_AUPLL:
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freq = HAL_CRU_GetPllV1Freq(&AUPLL);
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s_aupllFreq = freq;
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return freq;
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case PLL_PPLL:
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freq = HAL_CRU_GetPllV1Freq(&PPLL);
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s_ppllFreq = freq;
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return freq;
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case PLL_GPLL:
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freq = HAL_CRU_GetPllV1Freq(&GPLL);
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s_gpllFreq = freq;
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return s_gpllFreq;
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case CCLK_EMMC:
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case SCLK_SFC:
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case CCLK_SRC_SDIO:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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pRate = s_gpllFreq;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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pRate = s_cpllFreq;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
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pRate = PLL_INPUT_OSC_RATE;
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}
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return pRate / HAL_CRU_ClkGetDiv(clkDiv) ;
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case BCLK_EMMC:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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pRate = s_gpllFreq;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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pRate = s_cpllFreq;
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}
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return pRate / HAL_CRU_ClkGetDiv(clkDiv) ;
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case CLK_REF_PIPE_PHY0:
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case CLK_REF_PIPE_PHY1:
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case CLK_REF_PIPE_PHY2:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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return PLL_INPUT_OSC_RATE;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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return s_ppllFreq / HAL_CRU_ClkGetDiv(clkDiv) ;
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}
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default:
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break;
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}
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if ((clkMux == 0) && (clkDiv == 0)) {
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return 0;
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}
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if (clkDiv) {
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freq = pRate / (HAL_CRU_ClkGetDiv(clkDiv));
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} else {
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freq = pRate;
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}
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return freq;
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}
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/**
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* @brief Set clk freq.
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* @param clockName: CLOCK_Name id.
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* @param rate: clk rate.
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* @return HAL_Status.
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* @attention these APIs allow direct use in the HAL layer.
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*/
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HAL_Status
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EFIAPI
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HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate)
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{
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HAL_Status error = HAL_OK;
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uint32_t clkMux = CLK_GET_MUX(clockName);
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uint32_t clkDiv = CLK_GET_DIV(clockName);
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uint32_t mux = 0, div = 0, pRate = 0;
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if (!s_cpllFreq) {
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s_cpllFreq = HAL_CRU_GetPllV1Freq(&CPLL);
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}
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switch (clockName) {
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case PLL_LPLL:
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error = HAL_CRU_SetPllV1Freq(&LPLL, rate);
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s_lpllFreq = HAL_CRU_GetPllV1Freq(&LPLL);
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return error;
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case PLL_B0PLL:
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error = HAL_CRU_SetPllV1Freq(&B0PLL, rate);
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return error;
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case PLL_B1PLL:
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error = HAL_CRU_SetPllV1Freq(&B1PLL, rate);
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return error;
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case PLL_CPLL:
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error = HAL_CRU_SetPllV1Freq(&CPLL, rate);
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s_cpllFreq = HAL_CRU_GetPllV1Freq(&CPLL);
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return error;
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case PLL_PPLL:
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error = HAL_CRU_SetPllV1Freq(&PPLL, rate);
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s_ppllFreq = HAL_CRU_GetPllV1Freq(&PPLL);
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return error;
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case PLL_GPLL:
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error = HAL_CRU_SetPllV1Freq(&GPLL, rate);
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DEBUG ((DEBUG_INIT, "GPLL set rate: %d %x\n", rate, error));
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s_gpllFreq = HAL_CRU_GetPllV1Freq(&GPLL);
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return error;
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case PLL_NPLL:
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error = HAL_CRU_SetPllV1Freq(&NPLL, rate);
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s_npllFreq = HAL_CRU_GetPllV1Freq(&NPLL);
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return error;
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case PLL_AUPLL:
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error = HAL_CRU_SetPllV1Freq(&AUPLL, rate);
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s_aupllFreq = HAL_CRU_GetPllV1Freq(&AUPLL);
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return error;
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case PLL_V0PLL:
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error = HAL_CRU_SetPllV1Freq(&V0PLL, rate);
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s_v0pllFreq = HAL_CRU_GetPllV1Freq(&V0PLL);
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return error;
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case CCLK_EMMC:
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case SCLK_SFC:
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case CCLK_SRC_SDIO:
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if (PLL_INPUT_OSC_RATE % rate == 0) {
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pRate = PLL_INPUT_OSC_RATE;
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mux = 2;
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} else if (s_cpllFreq % rate == 0){
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pRate = s_cpllFreq;
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mux = 1;
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} else {
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pRate = s_gpllFreq;
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mux = 0;
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}
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break;
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case BCLK_EMMC:
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if (s_cpllFreq % rate == 0){
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pRate = s_cpllFreq;
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mux = 1;
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} else {
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pRate = s_gpllFreq;
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mux = 0;
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}
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break;
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case CLK_REF_PIPE_PHY0:
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case CLK_REF_PIPE_PHY1:
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case CLK_REF_PIPE_PHY2:
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if (rate == PLL_INPUT_OSC_RATE) {
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HAL_CRU_ClkSetMux(clkMux, 0);
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HAL_CRU_ClkSetDiv(clkDiv, 0);
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} else {
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div = HAL_DIV_ROUND_UP(s_ppllFreq, rate);
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HAL_CRU_ClkSetDiv(clkDiv, div);
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HAL_CRU_ClkSetMux(clkMux, 1);
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}
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return HAL_OK;
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default:
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break;
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}
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if ((clkMux == 0) && (clkDiv == 0)) {
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return HAL_INVAL;
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}
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div = HAL_DIV_ROUND_UP(pRate, rate);
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if (clkMux) {
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HAL_CRU_ClkSetMux(clkMux, mux);
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}
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if (clkDiv) {
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HAL_CRU_ClkSetDiv(clkDiv, div);
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}
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return HAL_OK;
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}
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/** @} */
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/** @} */
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/** @} */
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