/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include "Include/Library/CruLib.h"
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#include <Library/DebugLib.h>
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/** @addtogroup RK_HAL_Driver
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* @{
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*/
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/** @addtogroup CRU
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* @{
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*/
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/** @defgroup CRU_Private_Definition Private Definition
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* @{
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*/
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/********************* Private MACRO Definition ******************************/
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/********************* Private Structure Definition **************************/
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static struct PLL_CONFIG PLL_TABLE[] = {
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/* _mhz, _refDiv, _fbDiv, _postdDv1, _postDiv2, _dsmpd, _frac */
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RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
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RK_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
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RK_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
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RK_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
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RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
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RK_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
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RK_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
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RK_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
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{ /* sentinel */ },
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};
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static struct PLL_SETUP APLL = {
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.conOffset0 = &(CRU->APLL_CON[0]),
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.conOffset1 = &(CRU->APLL_CON[1]),
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.conOffset2 = &(CRU->APLL_CON[2]),
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.conOffset3 = &(CRU->APLL_CON[3]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 0,
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.lockShift = 10,
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.modeMask = 0x3,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP CPLL = {
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.conOffset0 = &(CRU->CPLL_CON[0]),
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.conOffset1 = &(CRU->CPLL_CON[1]),
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.conOffset2 = &(CRU->CPLL_CON[2]),
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.conOffset3 = &(CRU->CPLL_CON[3]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 4,
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.lockShift = 10,
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.modeMask = 0x3 << 4,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP GPLL = {
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.conOffset0 = &(CRU->GPLL_CON[0]),
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.conOffset1 = &(CRU->GPLL_CON[1]),
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.conOffset2 = &(CRU->GPLL_CON[2]),
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.conOffset3 = &(CRU->GPLL_CON[3]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 6,
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.lockShift = 10,
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.modeMask = 0x3 << 6,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP NPLL = {
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.conOffset0 = &(CRU->NPLL_CON[0]),
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.conOffset1 = &(CRU->NPLL_CON[1]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 10,
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.lockShift = 10,
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.modeMask = 0x3 << 10,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP VPLL = {
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.conOffset0 = &(CRU->VPLL_CON[0]),
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.conOffset1 = &(CRU->VPLL_CON[1]),
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.modeOffset = &(CRU->MODE_CON00),
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.modeShift = 12,
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.lockShift = 10,
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.modeMask = 0x3 << 12,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP PPLL = {
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.conOffset0 = &(PMUCRU->PPLL_CON[0]),
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.conOffset1 = &(PMUCRU->PPLL_CON[1]),
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.conOffset2 = &(PMUCRU->PPLL_CON[2]),
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.conOffset3 = &(PMUCRU->PPLL_CON[3]),
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.modeOffset = &(PMUCRU->MODE_CON00),
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.modeShift = 0,
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.lockShift = 10,
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.modeMask = 0x3 << 0,
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.rateTable = PLL_TABLE,
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};
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static struct PLL_SETUP HPLL = {
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.conOffset0 = &(PMUCRU->HPLL_CON[0]),
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.conOffset1 = &(PMUCRU->HPLL_CON[1]),
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.conOffset2 = &(PMUCRU->HPLL_CON[2]),
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.conOffset3 = &(PMUCRU->HPLL_CON[3]),
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.modeOffset = &(PMUCRU->MODE_CON00),
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.modeShift = 2,
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.lockShift = 10,
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.modeMask = 0x3 << 2,
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.rateTable = PLL_TABLE,
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};
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/********************* Private Variable Definition ***************************/
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static uint32_t s_apllFreq;
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static uint32_t s_cpllFreq;
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static uint32_t s_gpllFreq = 1188 * 1000 * 1000;
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static uint32_t s_npllFreq;
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static uint32_t s_vpllFreq;
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static uint32_t s_ppllFreq;
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static uint32_t s_hpllFreq;
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static uint32_t s_clk_gmac_xpcs_mii;
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static uint32_t s_clk_gmac_in;
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/********************* Private Function Definition ***************************/
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/** @} */
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/********************* Public Function Definition ****************************/
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/** @defgroup CRU_Exported_Functions_Group5 Other Functions
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* @{
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*/
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/**
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* @brief Get frac clk freq.
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* @param clockName: CLOCK_Name id
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* @return clk rate.
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* How to calculate the Frac clk divider:
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* numerator is frac register[31:16]
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* denominator is frac register[15:0]
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* clk rate = pRate * numerator / denominator
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* for a better jitter, pRate > 20 * rate
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*/
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static uint32_t HAL_CRU_ClkFracGetFreq(eCLOCK_Name clockName)
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{
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uint32_t freq = 0;
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uint32_t muxSrc = 0, mux = CLK_GET_MUX(clockName);
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uint32_t divSrc = 0, divFrac = 0;
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uint32_t n, m, pRate;
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switch (clockName) {
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case CLK_UART1:
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muxSrc = CLK_GET_MUX(CLK_UART1_SRC);
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divSrc = CLK_GET_DIV(CLK_UART1_SRC);
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divFrac = CLK_GET_DIV(CLK_UART1_FRAC);
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break;
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case CLK_UART2:
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muxSrc = CLK_GET_MUX(CLK_UART2_SRC);
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divSrc = CLK_GET_DIV(CLK_UART2_SRC);
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divFrac = CLK_GET_DIV(CLK_UART2_FRAC);
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break;
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case CLK_UART3:
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muxSrc = CLK_GET_MUX(CLK_UART3_SRC);
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divSrc = CLK_GET_DIV(CLK_UART3_SRC);
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divFrac = CLK_GET_DIV(CLK_UART3_FRAC);
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break;
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case CLK_UART4:
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muxSrc = CLK_GET_MUX(CLK_UART4_SRC);
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divSrc = CLK_GET_DIV(CLK_UART4_SRC);
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divFrac = CLK_GET_DIV(CLK_UART4_FRAC);
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break;
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case CLK_UART5:
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muxSrc = CLK_GET_MUX(CLK_UART5_SRC);
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divSrc = CLK_GET_DIV(CLK_UART5_SRC);
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divFrac = CLK_GET_DIV(CLK_UART5_FRAC);
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break;
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case CLK_UART6:
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muxSrc = CLK_GET_MUX(CLK_UART6_SRC);
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divSrc = CLK_GET_DIV(CLK_UART6_SRC);
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divFrac = CLK_GET_DIV(CLK_UART6_FRAC);
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break;
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case CLK_UART7:
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muxSrc = CLK_GET_MUX(CLK_UART7_SRC);
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divSrc = CLK_GET_DIV(CLK_UART7_SRC);
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divFrac = CLK_GET_DIV(CLK_UART7_FRAC);
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break;
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case CLK_UART8:
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muxSrc = CLK_GET_MUX(CLK_UART8_SRC);
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divSrc = CLK_GET_DIV(CLK_UART8_SRC);
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divFrac = CLK_GET_DIV(CLK_UART8_FRAC);
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break;
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case CLK_UART9:
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muxSrc = CLK_GET_MUX(CLK_UART9_SRC);
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divSrc = CLK_GET_DIV(CLK_UART9_SRC);
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divFrac = CLK_GET_DIV(CLK_UART9_FRAC);
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break;
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default:
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return 0;
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}
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n = (CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] & 0xffff0000) >> 16;
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m = CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] & 0x0000ffff;
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if (HAL_CRU_ClkGetMux(muxSrc)) {
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pRate = s_cpllFreq / HAL_CRU_ClkGetDiv(divSrc);
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} else {
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pRate = s_gpllFreq / HAL_CRU_ClkGetDiv(divSrc);
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}
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if (HAL_CRU_ClkGetMux(mux) == 0) {
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freq = pRate;
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} else if (HAL_CRU_ClkGetMux(mux) == 1) {
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freq = (pRate / m) * n;
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} else if (HAL_CRU_ClkGetMux(mux) == 2) {
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freq = PLL_INPUT_OSC_RATE;
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}
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return freq;
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}
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/**
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* @brief Set frac clk freq.
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* @param clockName: CLOCK_Name id.
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* @param rate: clk set rate
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* @return HAL_Status.
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* How to calculate the Frac clk divider:
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* if pRate > 20 * rate, select frac divider
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* else select normal divider, but the clk rate may be not accurate
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*/
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static HAL_Status HAL_CRU_ClkFracSetFreq(eCLOCK_Name clockName, uint32_t rate)
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{
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uint32_t muxSrc, mux = CLK_GET_MUX(clockName);
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uint32_t divSrc, divFrac;
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uint32_t n = 0, m = 0;
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uint32_t gateId, fracGateId;
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switch (clockName) {
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case CLK_UART1:
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muxSrc = CLK_GET_MUX(CLK_UART1_SRC);
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divSrc = CLK_GET_DIV(CLK_UART1_SRC);
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divFrac = CLK_GET_DIV(CLK_UART1_FRAC);
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gateId = CLK_UART1_GATE;
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fracGateId = CLK_UART1_FRAC_GATE;
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break;
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case CLK_UART2:
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muxSrc = CLK_GET_MUX(CLK_UART2_SRC);
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divSrc = CLK_GET_DIV(CLK_UART2_SRC);
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divFrac = CLK_GET_DIV(CLK_UART2_FRAC);
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gateId = CLK_UART2_GATE;
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fracGateId = CLK_UART2_FRAC_GATE;
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break;
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case CLK_UART3:
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muxSrc = CLK_GET_MUX(CLK_UART3_SRC);
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divSrc = CLK_GET_DIV(CLK_UART3_SRC);
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divFrac = CLK_GET_DIV(CLK_UART3_FRAC);
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gateId = CLK_UART3_GATE;
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fracGateId = CLK_UART3_FRAC_GATE;
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break;
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case CLK_UART4:
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muxSrc = CLK_GET_MUX(CLK_UART4_SRC);
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divSrc = CLK_GET_DIV(CLK_UART4_SRC);
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divFrac = CLK_GET_DIV(CLK_UART4_FRAC);
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gateId = CLK_UART4_GATE;
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fracGateId = CLK_UART4_FRAC_GATE;
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break;
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case CLK_UART5:
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muxSrc = CLK_GET_MUX(CLK_UART5_SRC);
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divSrc = CLK_GET_DIV(CLK_UART5_SRC);
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divFrac = CLK_GET_DIV(CLK_UART5_FRAC);
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gateId = CLK_UART5_GATE;
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fracGateId = CLK_UART5_FRAC_GATE;
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break;
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case CLK_UART6:
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muxSrc = CLK_GET_MUX(CLK_UART6_SRC);
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divSrc = CLK_GET_DIV(CLK_UART6_SRC);
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divFrac = CLK_GET_DIV(CLK_UART6_FRAC);
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gateId = CLK_UART6_GATE;
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fracGateId = CLK_UART6_FRAC_GATE;
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break;
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case CLK_UART7:
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muxSrc = CLK_GET_MUX(CLK_UART7_SRC);
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divSrc = CLK_GET_DIV(CLK_UART7_SRC);
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divFrac = CLK_GET_DIV(CLK_UART7_FRAC);
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gateId = CLK_UART7_GATE;
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fracGateId = CLK_UART7_FRAC_GATE;
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break;
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case CLK_UART8:
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muxSrc = CLK_GET_MUX(CLK_UART8_SRC);
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divSrc = CLK_GET_DIV(CLK_UART8_SRC);
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divFrac = CLK_GET_DIV(CLK_UART8_FRAC);
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gateId = CLK_UART8_GATE;
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fracGateId = CLK_UART8_FRAC_GATE;
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break;
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case CLK_UART9:
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muxSrc = CLK_GET_MUX(CLK_UART9_SRC);
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divSrc = CLK_GET_DIV(CLK_UART9_SRC);
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divFrac = CLK_GET_DIV(CLK_UART9_FRAC);
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gateId = CLK_UART9_GATE;
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fracGateId = CLK_UART9_FRAC_GATE;
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break;
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default:
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return HAL_INVAL;
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}
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HAL_CRU_ClkEnable(gateId);
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HAL_CRU_ClkEnable(fracGateId);
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if (PLL_INPUT_OSC_RATE == rate) {
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HAL_CRU_ClkSetMux(mux, 2);
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HAL_CRU_ClkDisable(gateId);
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} else if ((!(s_gpllFreq % rate)) && ((s_gpllFreq / rate) < 31)) {
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HAL_CRU_ClkSetDiv(divSrc, s_gpllFreq / rate);
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HAL_CRU_ClkSetMux(muxSrc, 0);
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HAL_CRU_ClkSetMux(mux, 0);
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HAL_CRU_ClkDisable(fracGateId);
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} else if ((!(s_cpllFreq % rate)) && ((s_cpllFreq / rate) < 31)) {
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HAL_CRU_ClkSetDiv(divSrc, s_cpllFreq / rate);
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HAL_CRU_ClkSetMux(muxSrc, 1);
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HAL_CRU_ClkSetMux(mux, 0);
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HAL_CRU_ClkDisable(fracGateId);
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} else {
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HAL_CRU_FracdivGetConfig(rate, s_gpllFreq, &n, &m);
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HAL_CRU_ClkSetDiv(divSrc, 1);
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HAL_CRU_ClkSetMux(muxSrc, 0);
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CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] = (n << 16) | m;
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HAL_CRU_ClkSetMux(mux, 1);
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}
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return HAL_OK;
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}
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/**
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* @brief Get gmac clk freq.
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* @param clockName: CLOCK_Name id
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* @return clk rate.
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*/
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static uint32_t HAL_CRU_ClkGmacGetFreq(eCLOCK_Name clockName)
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{
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uint32_t clkMux = CLK_GET_MUX(clockName);
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uint32_t clkDiv = CLK_GET_DIV(clockName);
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uint32_t freq;
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switch (clockName) {
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case ACLK_PHP:
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case ACLK_USB:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = 297000000;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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freq = 198000000;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
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freq = 99000000;
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} else {
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freq = PLL_INPUT_OSC_RATE;
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}
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return freq;
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case HCLK_PHP:
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case HCLK_USB:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = 148500000;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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freq = 99000000;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
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freq = 74250000;
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} else {
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freq = PLL_INPUT_OSC_RATE;
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}
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return freq;
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case PCLK_PHP:
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freq = HAL_CRU_ClkGmacGetFreq(ACLK_PHP) / (HAL_CRU_ClkGetDiv(clkDiv));
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return freq;
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case PCLK_USB:
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freq = HAL_CRU_ClkGmacGetFreq(ACLK_USB) / (HAL_CRU_ClkGetDiv(clkDiv));
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return freq;
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case CLK_MAC0_2TOP:
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case CLK_MAC1_2TOP:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = 125000000;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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freq = 50000000;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
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freq = 25000000;
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} else {
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freq = HAL_CRU_ClkGetFreq(PLL_PPLL);
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}
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return freq;
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case CLK_MAC0_OUT:
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case CLK_MAC1_OUT:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = 125000000;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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freq = 50000000;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
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freq = 25000000;
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} else {
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freq = PLL_INPUT_OSC_RATE;
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}
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return freq;
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case CLK_GMAC0_PTP_REF:
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case CLK_GMAC1_PTP_REF:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = 62500;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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freq = 100000000;
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} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
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freq = 50000000;
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} else {
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freq = PLL_INPUT_OSC_RATE;
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}
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return freq;
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case SCLK_GMAC0_RGMII_SPEED:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP);
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP);
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} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 50;
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} else {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 5;
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}
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return freq;
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case SCLK_GMAC1_RGMII_SPEED:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP);
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP);
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} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 50;
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} else {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 5;
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}
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return freq;
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case SCLK_GMAC0_RMII_SPEED:
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if (HAL_CRU_ClkGetMux(clkMux)) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 2;
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} else {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 20;
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}
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return freq;
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case SCLK_GMAC1_RMII_SPEED:
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if (HAL_CRU_ClkGetMux(clkMux)) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 2;
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} else {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 20;
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}
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return freq;
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case SCLK_GMAC0:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP);
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} else {
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freq = s_clk_gmac_in;
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}
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return freq;
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case SCLK_GMAC1:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP);
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} else {
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freq = s_clk_gmac_in;
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}
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return freq;
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case SCLK_GMAC0_RX_TX:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = HAL_CRU_ClkGetFreq(SCLK_GMAC0_RGMII_SPEED);
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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freq = HAL_CRU_ClkGetFreq(SCLK_GMAC0_RMII_SPEED);
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} else {
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freq = s_clk_gmac_xpcs_mii;
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}
|
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return freq;
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case SCLK_GMAC1_RX_TX:
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if (HAL_CRU_ClkGetMux(clkMux) == 0) {
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freq = HAL_CRU_ClkGetFreq(SCLK_GMAC1_RGMII_SPEED);
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} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
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freq = HAL_CRU_ClkGetFreq(SCLK_GMAC1_RMII_SPEED);
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} else {
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freq = s_clk_gmac_xpcs_mii;
|
}
|
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return freq;
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default:
|
|
return 0;
|
}
|
}
|
|
/**
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* @brief Set gmac clk freq.
|
* @param clockName: CLOCK_Name id.
|
* @param rate: clk set rate
|
* @return HAL_Status.
|
*/
|
static HAL_Status HAL_CRU_ClkGmacSetFreq(eCLOCK_Name clockName, uint32_t rate)
|
{
|
uint32_t clkMux = CLK_GET_MUX(clockName);
|
uint32_t clkDiv = CLK_GET_DIV(clockName);
|
uint32_t mux = 0, div = 0;
|
|
switch (clockName) {
|
case ACLK_PHP:
|
case ACLK_USB:
|
if (rate >= 297000000) {
|
mux = 0;
|
} else if (rate >= 198000000) {
|
mux = 1;
|
} else if (rate >= 99000000) {
|
mux = 2;
|
} else {
|
mux = 3;
|
}
|
break;
|
case HCLK_PHP:
|
case HCLK_USB:
|
if (rate >= 148500000) {
|
mux = 0;
|
} else if (rate >= 99000000) {
|
mux = 1;
|
} else if (rate >= 74250000) {
|
mux = 2;
|
} else {
|
mux = 3;
|
}
|
break;
|
case PCLK_PHP:
|
div = HAL_DIV_ROUND_UP(HAL_CRU_ClkGmacGetFreq(ACLK_PHP), rate);
|
|
break;
|
case PCLK_USB:
|
div = HAL_DIV_ROUND_UP(HAL_CRU_ClkGmacGetFreq(ACLK_USB), rate);
|
|
break;
|
|
case CLK_MAC0_2TOP:
|
case CLK_MAC1_2TOP:
|
case CLK_MAC0_OUT:
|
case CLK_MAC1_OUT:
|
if (rate == 125000000) {
|
mux = 0;
|
} else if (rate == 50000000) {
|
mux = 1;
|
} else if (rate == 25000000) {
|
mux = 2;
|
} else {
|
mux = 3;
|
}
|
|
break;
|
|
case CLK_GMAC0_PTP_REF:
|
case CLK_GMAC1_PTP_REF:
|
if (rate == 62500) {
|
mux = 0;
|
} else if (rate == 100000000) {
|
mux = 1;
|
} else if (rate == 50000000) {
|
mux = 2;
|
} else {
|
mux = 3;
|
}
|
|
break;
|
|
case SCLK_GMAC0_RGMII_SPEED:
|
if (rate == HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 50) {
|
mux = 2;
|
} else if (rate == HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 5) {
|
mux = 3;
|
} else {
|
mux = 0;
|
}
|
break;
|
|
case SCLK_GMAC1_RGMII_SPEED:
|
if (rate == HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 50) {
|
mux = 2;
|
} else if (rate == HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 5) {
|
mux = 3;
|
} else {
|
mux = 0;
|
}
|
break;
|
|
case SCLK_GMAC0_RMII_SPEED:
|
if (rate == HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 2) {
|
mux = 1;
|
} else {
|
mux = 0;
|
}
|
break;
|
|
case SCLK_GMAC1_RMII_SPEED:
|
if (rate == HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 2) {
|
mux = 1;
|
} else {
|
mux = 0;
|
}
|
break;
|
case SCLK_GMAC0:
|
if (rate == HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP)) {
|
mux = 0;
|
} else {
|
mux = 1;
|
}
|
break;
|
|
case SCLK_GMAC1:
|
if (rate == HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP)) {
|
mux = 0;
|
} else {
|
mux = 1;
|
}
|
break;
|
|
case SCLK_GMAC0_RX_TX:
|
if (rate == HAL_CRU_ClkGetFreq(SCLK_GMAC0_RGMII_SPEED)) {
|
mux = 0;
|
} else if (rate == HAL_CRU_ClkGetFreq(SCLK_GMAC0_RMII_SPEED)) {
|
mux = 1;
|
} else {
|
mux = 2;
|
}
|
break;
|
case SCLK_GMAC1_RX_TX:
|
if (rate == HAL_CRU_ClkGetFreq(SCLK_GMAC1_RGMII_SPEED)) {
|
mux = 0;
|
} else if (rate == HAL_CRU_ClkGetFreq(SCLK_GMAC1_RMII_SPEED)) {
|
mux = 1;
|
} else {
|
mux = 2;
|
}
|
break;
|
default:
|
|
return HAL_INVAL;
|
}
|
|
if (clkMux) {
|
HAL_CRU_ClkSetMux(clkMux, mux);
|
}
|
if (clkDiv) {
|
HAL_CRU_ClkSetDiv(clkDiv, div);
|
}
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief Get mmc clk freq.
|
* @param clockName: CLOCK_Name id
|
* @return clk rate.
|
*/
|
static uint32_t HAL_CRU_ClkMmcGetFreq(eCLOCK_Name clockName)
|
{
|
uint32_t clkMux = CLK_GET_MUX(clockName);
|
uint32_t freq;
|
|
switch (clockName) {
|
case BCLK_EMMC:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = 198000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = 148500000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
freq = 125000000;
|
}
|
|
return freq;
|
case CCLK_EMMC:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = PLL_INPUT_OSC_RATE;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = 198000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
freq = 148500000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 3) {
|
freq = 100000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 4) {
|
freq = 50000000;
|
} else {
|
freq = 375000;
|
}
|
|
return freq;
|
|
case DCLK_SDMMC_BUFFER:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = 99000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = 74250000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
freq = 50000000;
|
}
|
|
return freq;
|
|
case CLK_SDMMC0:
|
case CLK_SDMMC1:
|
case CLK_SDMMC2:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = PLL_INPUT_OSC_RATE;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = 396000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
freq = 297000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 3) {
|
freq = 100000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 4) {
|
freq = 50000000;
|
} else {
|
freq = 750000;
|
}
|
|
return freq;
|
|
default:
|
|
return 0;
|
}
|
}
|
|
/**
|
* @brief Set mmc clk freq.
|
* @param clockName: CLOCK_Name id.
|
* @param rate: clk set rate
|
* @return HAL_Status.
|
*/
|
static HAL_Status HAL_CRU_ClkMmcSetFreq(eCLOCK_Name clockName, uint32_t rate)
|
{
|
uint32_t clkMux = CLK_GET_MUX(clockName);
|
uint32_t mux = 0;
|
|
switch (clockName) {
|
case BCLK_EMMC:
|
if (rate >= 198000000) {
|
mux = 0;
|
} else if (rate >= 148000000) {
|
mux = 1;
|
} else {
|
mux = 2;
|
}
|
break;
|
|
case CCLK_EMMC:
|
if (rate >= 198000000) {
|
mux = 1;
|
} else if (rate >= 148000000) {
|
mux = 2;
|
} else if (rate >= 100000000) {
|
mux = 3;
|
} else if (rate >= 50000000) {
|
mux = 4;
|
} else if (rate >= 24000000) {
|
mux = 0;
|
} else {
|
mux = 5;
|
}
|
break;
|
|
case DCLK_SDMMC_BUFFER:
|
if (rate >= 99000000) {
|
mux = 0;
|
} else if (rate >= 74000000) {
|
mux = 1;
|
} else {
|
mux = 2;
|
}
|
break;
|
|
case CLK_SDMMC0:
|
case CLK_SDMMC1:
|
case CLK_SDMMC2:
|
if (rate >= 396000000) {
|
mux = 1;
|
} else if (rate >= 297000000) {
|
mux = 2;
|
} else if (rate >= 100000000) {
|
mux = 3;
|
} else if (rate >= 50000000) {
|
mux = 4;
|
} else if (rate >= 24000000) {
|
mux = 0;
|
} else {
|
mux = 5;
|
}
|
break;
|
|
default:
|
|
return 0;
|
}
|
if (clkMux) {
|
HAL_CRU_ClkSetMux(clkMux, mux);
|
}
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief Get clk freq.
|
* @param clockName: CLOCK_Name id.
|
* @return rate.
|
* @attention these APIs allow direct use in the HAL layer.
|
*/
|
uint32_t
|
EFIAPI
|
HAL_CRU_ClkGetFreq(eCLOCK_Name clockName)
|
{
|
uint32_t clkMux = CLK_GET_MUX(clockName);
|
uint32_t clkDiv = CLK_GET_DIV(clockName);
|
uint32_t pRate = 0, freq;
|
|
if (!s_cpllFreq) {
|
s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL);
|
}
|
|
switch (clockName) {
|
case PLL_APLL:
|
freq = HAL_CRU_GetPllFreq(&APLL);
|
s_apllFreq = freq;
|
|
return freq;
|
case PLL_CPLL:
|
freq = HAL_CRU_GetPllFreq(&CPLL);
|
s_cpllFreq = freq;
|
|
return freq;
|
case PLL_NPLL:
|
freq = HAL_CRU_GetPllFreq(&NPLL);
|
s_npllFreq = freq;
|
|
return freq;
|
case PLL_VPLL:
|
freq = HAL_CRU_GetPllFreq(&VPLL);
|
s_vpllFreq = freq;
|
|
return freq;
|
case PLL_HPLL:
|
freq = HAL_CRU_GetPllFreq(&HPLL);
|
s_hpllFreq = freq;
|
|
return freq;
|
case PLL_PPLL:
|
freq = HAL_CRU_GetPllFreq(&PPLL);
|
s_ppllFreq = freq;
|
|
return freq;
|
case PLL_GPLL:
|
freq = HAL_CRU_GetPllFreq(&GPLL);
|
s_gpllFreq = freq;
|
|
return s_gpllFreq;
|
case CLK_WDT:
|
|
return PLL_INPUT_OSC_RATE;
|
case CLK_I2C:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = s_gpllFreq / 6;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = s_gpllFreq / 12;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
freq = PLL_INPUT_OSC_RATE;
|
} else {
|
freq = s_cpllFreq / 10;
|
}
|
|
return freq;
|
case CLK_PWM1:
|
case CLK_PWM2:
|
case CLK_PWM3:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = s_gpllFreq / 12;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = PLL_INPUT_OSC_RATE;
|
} else {
|
freq = s_cpllFreq / 10;
|
}
|
|
return freq;
|
case CLK_SPI0:
|
case CLK_SPI1:
|
case CLK_SPI2:
|
case CLK_SPI3:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = s_gpllFreq / 6;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = PLL_INPUT_OSC_RATE;
|
} else {
|
freq = s_cpllFreq / 10;
|
}
|
|
return freq;
|
case CLK_UART1:
|
case CLK_UART2:
|
case CLK_UART3:
|
case CLK_UART4:
|
case CLK_UART5:
|
case CLK_UART6:
|
case CLK_UART7:
|
case CLK_UART8:
|
case CLK_UART9:
|
freq = HAL_CRU_ClkFracGetFreq(clockName);
|
|
return freq;
|
case CLK_CAN0:
|
case CLK_CAN1:
|
case CLK_CAN2:
|
if (HAL_CRU_ClkGetMux(clkMux)) {
|
pRate = s_cpllFreq;
|
} else {
|
pRate = s_gpllFreq;
|
}
|
|
break;
|
|
case CLK_TSADC_TSEN:
|
if (HAL_CRU_ClkGetMux(clkMux)) {
|
pRate = s_gpllFreq / 12;
|
} else {
|
pRate = PLL_INPUT_OSC_RATE;
|
}
|
|
break;
|
case CLK_TSADC:
|
pRate = HAL_CRU_ClkGetFreq(CLK_TSADC_TSEN);
|
|
break;
|
|
case SCLK_SFC:
|
if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = 50000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
freq = 75000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 3) {
|
freq = 100000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 4) {
|
freq = 125000000;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 5) {
|
freq = 150000000;
|
} else {
|
freq = PLL_INPUT_OSC_RATE;
|
}
|
|
return freq;
|
case ACLK_USB:
|
case HCLK_USB:
|
case PCLK_USB:
|
case ACLK_PHP:
|
case HCLK_PHP:
|
case PCLK_PHP:
|
case CLK_MAC0_2TOP:
|
case CLK_MAC1_2TOP:
|
case CLK_MAC0_OUT:
|
case CLK_MAC1_OUT:
|
case CLK_GMAC0_PTP_REF:
|
case CLK_GMAC1_PTP_REF:
|
case SCLK_GMAC0_RGMII_SPEED:
|
case SCLK_GMAC1_RGMII_SPEED:
|
case SCLK_GMAC0_RMII_SPEED:
|
case SCLK_GMAC1_RMII_SPEED:
|
case SCLK_GMAC0_RX_TX:
|
case SCLK_GMAC1_RX_TX:
|
freq = HAL_CRU_ClkGmacGetFreq(clockName);
|
|
return freq;
|
|
case BCLK_EMMC:
|
case CCLK_EMMC:
|
case DCLK_SDMMC_BUFFER:
|
case CLK_SDMMC0:
|
case CLK_SDMMC1:
|
case CLK_SDMMC2:
|
freq = HAL_CRU_ClkMmcGetFreq(clockName);
|
|
return freq;
|
|
case ACLK_SECURE_FLASH:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = s_gpllFreq / 6;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = s_gpllFreq / 8;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
freq = s_gpllFreq / 10;
|
} else {
|
freq = PLL_INPUT_OSC_RATE;
|
}
|
|
return freq;
|
|
case HCLK_SECURE_FLASH:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = s_gpllFreq / 8;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = s_gpllFreq / 10;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
freq = s_gpllFreq / 16;
|
} else {
|
freq = PLL_INPUT_OSC_RATE;
|
}
|
|
return freq;
|
|
case ACLK_PIPE:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
freq = s_gpllFreq / 3;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
freq = s_gpllFreq / 4;
|
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
freq = s_gpllFreq / 6;
|
} else {
|
freq = PLL_INPUT_OSC_RATE;
|
}
|
|
return freq;
|
|
case PCLK_PIPE:
|
pRate = HAL_CRU_ClkGetFreq(ACLK_PIPE);
|
|
break;
|
|
case CLK_PCIEPHY0_REF:
|
case CLK_PCIEPHY1_REF:
|
case CLK_PCIEPHY2_REF:
|
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
|
pRate = 0;
|
} else {
|
pRate = s_ppllFreq / 2;
|
}
|
|
break;
|
|
default:
|
break;
|
}
|
|
if ((clkMux == 0) && (clkDiv == 0)) {
|
return 0;
|
}
|
|
if (clkDiv) {
|
freq = pRate / (HAL_CRU_ClkGetDiv(clkDiv));
|
} else {
|
freq = pRate;
|
}
|
|
return freq;
|
}
|
|
/**
|
* @brief Set clk freq.
|
* @param clockName: CLOCK_Name id.
|
* @param rate: clk rate.
|
* @return HAL_Status.
|
* @attention these APIs allow direct use in the HAL layer.
|
*/
|
HAL_Status
|
EFIAPI
|
HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate)
|
{
|
HAL_Status error = HAL_OK;
|
uint32_t clkMux = CLK_GET_MUX(clockName);
|
uint32_t clkDiv = CLK_GET_DIV(clockName);
|
uint32_t mux = 0, div = 0, pRate = 0;
|
|
if (!s_cpllFreq) {
|
s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL);
|
}
|
|
switch (clockName) {
|
case PLL_APLL:
|
|
return error;
|
case PLL_CPLL:
|
error = HAL_CRU_SetPllFreq(&CPLL, rate);
|
s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL);
|
|
return error;
|
case PLL_HPLL:
|
|
return error;
|
case PLL_GPLL:
|
error = HAL_CRU_SetPllFreq(&GPLL, rate);
|
DEBUG ((DEBUG_INIT, "GPLL set rate: %d %x\n", rate, error));
|
s_gpllFreq = HAL_CRU_GetPllFreq(&GPLL);
|
return error;
|
|
case CLK_UART1:
|
case CLK_UART2:
|
case CLK_UART3:
|
case CLK_UART4:
|
case CLK_UART5:
|
case CLK_UART6:
|
case CLK_UART7:
|
case CLK_UART8:
|
case CLK_UART9:
|
error = HAL_CRU_ClkFracSetFreq(clockName, rate);
|
|
return error;
|
|
case CLK_CAN0:
|
case CLK_CAN1:
|
case CLK_CAN2:
|
if (s_cpllFreq % rate == 0) {
|
pRate = s_cpllFreq;
|
mux = 1;
|
} else {
|
pRate = s_gpllFreq;
|
mux = 0;
|
}
|
|
break;
|
|
case CLK_TSADC_TSEN:
|
if (PLL_INPUT_OSC_RATE % rate == 0) {
|
pRate = PLL_INPUT_OSC_RATE;
|
mux = 0;
|
} else {
|
pRate = s_gpllFreq / 12;
|
mux = 1;
|
}
|
|
break;
|
case CLK_TSADC:
|
pRate = HAL_CRU_ClkGetFreq(CLK_TSADC_TSEN);
|
|
break;
|
case SCLK_SFC:
|
if (rate == 50000000) {
|
mux = 1;
|
} else if (rate == 75000000) {
|
mux = 2;
|
} else if (rate == 100000000) {
|
mux = 3;
|
} else if (rate == 125000000) {
|
mux = 4;
|
} else if (rate == 150000000) {
|
mux = 5;
|
} else {
|
mux = 0;
|
}
|
|
break;
|
case ACLK_USB:
|
case HCLK_USB:
|
case PCLK_USB:
|
case ACLK_PHP:
|
case HCLK_PHP:
|
case PCLK_PHP:
|
case CLK_MAC0_2TOP:
|
case CLK_MAC1_2TOP:
|
case CLK_MAC0_OUT:
|
case CLK_MAC1_OUT:
|
case CLK_GMAC0_PTP_REF:
|
case CLK_GMAC1_PTP_REF:
|
case SCLK_GMAC0_RGMII_SPEED:
|
case SCLK_GMAC1_RGMII_SPEED:
|
case SCLK_GMAC0_RMII_SPEED:
|
case SCLK_GMAC1_RMII_SPEED:
|
case SCLK_GMAC0_RX_TX:
|
case SCLK_GMAC1_RX_TX:
|
error = HAL_CRU_ClkGmacSetFreq(clockName, rate);
|
|
return error;
|
|
case BCLK_EMMC:
|
case CCLK_EMMC:
|
case DCLK_SDMMC_BUFFER:
|
case CLK_SDMMC0:
|
case CLK_SDMMC1:
|
case CLK_SDMMC2:
|
error = HAL_CRU_ClkMmcSetFreq(clockName, rate);
|
|
return error;
|
|
case ACLK_SECURE_FLASH:
|
if (rate >= 198000000) {
|
mux = 0;
|
} else if (rate >= 148000000) {
|
mux = 1;
|
} else if (rate >= 99000000) {
|
mux = 2;
|
} else {
|
mux = 3;
|
}
|
|
break;
|
|
case HCLK_SECURE_FLASH:
|
if (rate >= 148000000) {
|
mux = 0;
|
} else if (rate >= 99000000) {
|
mux = 1;
|
} else if (rate >= 74000000) {
|
mux = 2;
|
} else {
|
mux = 3;
|
}
|
|
break;
|
|
case ACLK_PIPE:
|
if (rate >= 396000000) {
|
mux = 0;
|
} else if (rate >= 297000000) {
|
mux = 1;
|
} else if (rate >= 198000000) {
|
mux = 2;
|
} else {
|
mux = 3;
|
}
|
|
break;
|
|
case PCLK_PIPE:
|
pRate = HAL_CRU_ClkGetFreq(ACLK_PIPE);
|
|
break;
|
|
case CLK_PCIEPHY0_REF:
|
case CLK_PCIEPHY1_REF:
|
case CLK_PCIEPHY2_REF:
|
pRate = s_ppllFreq / 2;
|
mux = 1;
|
|
break;
|
|
default:
|
break;
|
}
|
|
if ((clkMux == 0) && (clkDiv == 0)) {
|
return HAL_INVAL;
|
}
|
|
div = HAL_DIV_ROUND_UP(pRate, rate);
|
if (clkMux) {
|
HAL_CRU_ClkSetMux(clkMux, mux);
|
}
|
if (clkDiv) {
|
HAL_CRU_ClkSetDiv(clkDiv, div);
|
}
|
|
return HAL_OK;
|
}
|
|
/**
|
* @brief wdt glbrst enable.
|
* @param wdtType: wdt reset type.
|
* @return HAL_OK.
|
* @attention these APIs allow direct use in the HAL layer.
|
*/
|
HAL_Status
|
EFIAPI
|
HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType)
|
{
|
uint32_t mask = CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_MASK;
|
uint32_t val = 0;
|
|
switch (wdtType) {
|
case GLB_RST_FST_WDT0:
|
val |= (1 << CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_SHIFT);
|
break;
|
case GLB_RST_SND_WDT0:
|
break;
|
default:
|
|
return HAL_INVAL;
|
}
|
|
CRU->GLB_RST_CON = VAL_MASK_WE(mask, val);
|
|
return HAL_OK;
|
}
|
|
/** @} */
|
|
/** @} */
|
|
/** @} */
|
