/** @file
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*
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* Copyright (c) 2019 Linaro, Limited. All rights reserved.
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* Copyright (c) 2021 Arm
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <IndustryStandard/Bcm2711.h>
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#include "AcpiTables.h"
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/*
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* The following can be used to remove parenthesis from
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* defined macros that the compiler complains about.
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*/
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#define ISOLATE_ARGS(...) __VA_ARGS__
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#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
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#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
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#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
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#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
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DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
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{
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Scope (\_SB_)
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{
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Device(PCI0)
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{
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Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
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Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
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Name(_SEG, Zero) // PCI Segment Group number
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Name(_BBN, Zero) // PCI Base Bus Number
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Name(_CCA, 0) // Mark the PCI noncoherent
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// PCIe can only DMA to first 3GB with early SOC's
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// But we keep the restriction on the later ones
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// To avoid DMA translation problems.
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Name (_DMA, ResourceTemplate() {
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QWordMemory (ResourceProducer,
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,
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MinFixed,
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MaxFixed,
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NonCacheable,
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ReadWrite,
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0x0,
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0x0, // MIN
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0xbfffffff, // MAX
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0x0, // TRA
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0xc0000000, // LEN
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,
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,
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)
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})
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// PCI Routing Table
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Name(_PRT, Package() {
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Package (4) { 0x0000FFFF, 0, zero, 175 },
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Package (4) { 0x0000FFFF, 1, zero, 176 },
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Package (4) { 0x0000FFFF, 2, zero, 177 },
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Package (4) { 0x0000FFFF, 3, zero, 178 }
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})
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () { "linux-ecam-quirk-id", "bcm2711" },
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}
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})
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// Root complex resources
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Method (_CRS, 0, Serialized) {
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Name (RBUF, ResourceTemplate () {
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// bus numbers assigned to this root
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WordBusNumber (
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ResourceProducer,
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MinFixed, MaxFixed, PosDecode,
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0, // AddressGranularity
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0, // AddressMinimum - Minimum Bus Number
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255, // AddressMaximum - Maximum Bus Number
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0, // AddressTranslation - Set to 0
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256 // RangeLength - Number of Busses
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)
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// 32-bit mmio window in 64-bit addr
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QWordMemory (
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ResourceProducer, PosDecode,
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MinFixed, MaxFixed,
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NonCacheable, ReadWrite, // cacheable
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0x00000000, // Granularity
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0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
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1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
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SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
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2 // SANITIZED_PCIE_MMIO_LEN + 1
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,,,MMI1
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)
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// root port registers, not to be used if SMCCC is utilized
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QWordMemory (
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ResourceConsumer, ,
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MinFixed, MaxFixed,
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NonCacheable, ReadWrite, // cacheable
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0x00000000, // Granularity
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0xFD500000, // Root port begin
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0xFD509FFF, // Root port end
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0x00000000, // no translation
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0x0000A000, // size
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,,
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)
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}) // end Name(RBUF)
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// Work around ASL's inability to add in a resource definition
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// or for that matter compute the min,max,len properly
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CreateQwordField (RBUF, MMI1._MIN, MMIB)
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CreateQwordField (RBUF, MMI1._MAX, MMIE)
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CreateQwordField (RBUF, MMI1._TRA, MMIT)
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CreateQwordField (RBUF, MMI1._LEN, MMIL)
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Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
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Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
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Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
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Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
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Return (RBUF)
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} // end Method(_CRS)
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// OS Control Handoff
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Name(SUPP, Zero) // PCI _OSC Support Field value
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Name(CTRL, Zero) // PCI _OSC Control Field value
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// See [1] 6.2.10, [2] 4.5
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Method(_OSC,4) {
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// Note, This code is very similar to the code in the PCIe firmware
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// specification which can be used as a reference
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// Check for proper UUID
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If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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// Create DWord-adressable fields from the Capabilities Buffer
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CreateDWordField(Arg3,0,CDW1)
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CreateDWordField(Arg3,4,CDW2)
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CreateDWordField(Arg3,8,CDW3)
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// Save Capabilities DWord2 & 3
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Store(CDW2,SUPP)
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Store(CDW3,CTRL)
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// Mask out Native HotPlug
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And(CTRL,0x1E,CTRL)
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// Always allow native PME, AER (no dependencies)
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// Never allow SHPC (no SHPC controller in this system)
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And(CTRL,0x1D,CTRL)
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If(LNotEqual(Arg1,One)) { // Unknown revision
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Or(CDW1,0x08,CDW1)
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}
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If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
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Or(CDW1,0x10,CDW1)
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}
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// Update DWORD3 in the buffer
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Store(CTRL,CDW3)
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Return(Arg3)
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} Else {
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Or(CDW1,4,CDW1) // Unrecognized UUID
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Return(Arg3)
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}
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} // End _OSC
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} // PCI0
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} //end scope sb
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} //end definition block
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