/** @file
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*
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* RPi defines for constructing ACPI tables
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*
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* Copyright (c) 2020, Pete Batard <pete@akeo.ie>
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* Copyright (c) 2019, ARM Ltd. All rights reserved.
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* Copyright (c) 2018, Andrei Warkentin <andrey.warkentin@gmail.com>
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* Copyright (c) Microsoft Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __ACPITABLES_H__
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#define __ACPITABLES_H__
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#include <IndustryStandard/Acpi.h>
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// The ASL compiler can't perform arithmetic on MEMORY32FIXED ()
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// parameters so you can't pass a constant like BASE + OFFSET.
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// We therefore define a macro that can perform arithmetic base
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// address update with an offset.
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#define MEMORY32SETBASE(BufName, MemName, VarName, Offset) \
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CreateDwordField (^BufName, ^MemName._BAS, VarName) \
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Add (BCM2836_SOC_REGISTERS, Offset, VarName)
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#define EFI_ACPI_OEM_ID {'R','P','I','F','D','N'}
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#if (RPI_MODEL == 3)
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#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64 ('R','P','I','3',' ',' ',' ',' ')
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#elif (RPI_MODEL == 4)
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#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64 ('R','P','I','4',' ',' ',' ',' ')
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#endif
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#define EFI_ACPI_OEM_REVISION 0x00000200
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#define EFI_ACPI_CREATOR_ID SIGNATURE_32 ('E','D','K','2')
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#define EFI_ACPI_CREATOR_REVISION 0x00000300
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#define EFI_ACPI_VENDOR_ID SIGNATURE_32 ('R','P','I','F')
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// A macro to initialise the common header part of EFI ACPI tables as defined by
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// EFI_ACPI_DESCRIPTION_HEADER structure.
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#define ACPI_HEADER(Signature, Type, Revision) { \
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Signature, /* UINT32 Signature */ \
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sizeof (Type), /* UINT32 Length */ \
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Revision, /* UINT8 Revision */ \
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0, /* UINT8 Checksum */ \
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EFI_ACPI_OEM_ID, /* UINT8 OemId[6] */ \
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EFI_ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \
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EFI_ACPI_OEM_REVISION, /* UINT32 OemRevision */ \
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EFI_ACPI_CREATOR_ID, /* UINT32 CreatorId */ \
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EFI_ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \
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}
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#define EFI_ACPI_CSRT_REVISION 0x00000005
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#define EFI_ACPI_CSRT_DEVICE_ID_DMA 0x00000009 // Fixed id
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#define EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP 0x0 // Count up from 0
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#define RPI_DMA_CHANNEL_COUNT 10 // All 10 DMA channels are listed, including the reserved ones
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#define RPI_DMA_USED_CHANNEL_COUNT 5 // Use 5 DMA channels
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#if (RPI_MODEL == 3)
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#define RPI_SYSTEM_TIMER_BASE_ADDRESS 0x4000001C
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#elif (RPI_MODEL == 4)
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#define RPI_SYSTEM_TIMER_BASE_ADDRESS 0xFF80001C
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#endif
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#define EFI_ACPI_6_3_CSRT_REVISION 0x00000000
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typedef enum
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{
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EFI_ACPI_CSRT_RESOURCE_TYPE_RESERVED, // 0
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EFI_ACPI_CSRT_RESOURCE_TYPE_INTERRUPT, // 1
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EFI_ACPI_CSRT_RESOURCE_TYPE_TIMER, // 2
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EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, // 3
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EFI_ACPI_CSRT_RESOURCE_TYPE_CACHE, // 4
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}
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CSRT_RESOURCE_TYPE;
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typedef enum
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{
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EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, // 0
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EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CONTROLLER // 1
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}
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CSRT_DMA_SUBTYPE;
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//------------------------------------------------------------------------
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// CSRT Resource Group header 24 bytes long
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//------------------------------------------------------------------------
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typedef struct
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{
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UINT32 Length; // Length
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UINT32 VendorID; // 4 bytes
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UINT32 SubVendorId; // 4 bytes
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UINT16 DeviceId; // 2 bytes
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UINT16 SubdeviceId; // 2 bytes
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UINT16 Revision; // 2 bytes
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UINT16 Reserved; // 2 bytes
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UINT32 SharedInfoLength; // 4 bytes
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} EFI_ACPI_6_3_CSRT_RESOURCE_GROUP_HEADER;
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//------------------------------------------------------------------------
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// CSRT Resource Descriptor 12 bytes total
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//------------------------------------------------------------------------
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typedef struct
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{
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UINT32 Length; // 4 bytes
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UINT16 ResourceType; // 2 bytes
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UINT16 ResourceSubType; // 2 bytes
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UINT32 UID; // 4 bytes
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} EFI_ACPI_6_3_CSRT_RESOURCE_DESCRIPTOR_HEADER;
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//------------------------------------------------------------------------
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// Interrupts. These are specific to each platform
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//------------------------------------------------------------------------
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#if (RPI_MODEL == 3)
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#define BCM2836_V3D_BUS_INTERRUPT 0x2A
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#define BCM2836_DMA_INTERRUPT 0x3B
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#define BCM2836_SPI1_INTERRUPT 0x3D
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#define BCM2836_SPI2_INTERRUPT 0x3D
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#define BCM2836_HVS_INTERRUPT 0x41
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#define BCM2836_HDMI0_INTERRUPT 0x48
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#define BCM2836_HDMI1_INTERRUPT 0x49
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#define BCM2836_PV2_INTERRUPT 0x4A
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#define BCM2836_PV0_INTERRUPT 0x4D
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#define BCM2836_PV1_INTERRUPT 0x4E
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#define BCM2836_MBOX_INTERRUPT 0x61
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#define BCM2836_VCHIQ_INTERRUPT 0x62
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#define BCM2386_GPIO_INTERRUPT0 0x51
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#define BCM2386_GPIO_INTERRUPT1 0x52
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#define BCM2386_GPIO_INTERRUPT2 0x53
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#define BCM2386_GPIO_INTERRUPT3 0x54
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#define BCM2836_I2C1_INTERRUPT 0x55
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#define BCM2836_I2C2_INTERRUPT 0x55
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#define BCM2836_SPI0_INTERRUPT 0x56
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#define BCM2836_USB_INTERRUPT 0x29
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#define BCM2836_SDHOST_INTERRUPT 0x58
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#define BCM2836_MMCHS1_INTERRUPT 0x5E
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#define BCM2836_MINI_UART_INTERRUPT 0x3D
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#define BCM2836_PL011_UART_INTERRUPT 0x59
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#elif (RPI_MODEL == 4)
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#define BCM2836_V3D_BUS_INTERRUPT 0x2A
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#define BCM2836_DMA_INTERRUPT 0x3B
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#define BCM2836_SPI1_INTERRUPT 0x7D
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#define BCM2836_SPI2_INTERRUPT 0x7D
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#define BCM2836_HVS_INTERRUPT 0x41
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#define BCM2836_HDMI0_INTERRUPT 0x48
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#define BCM2836_HDMI1_INTERRUPT 0x49
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#define BCM2836_PV2_INTERRUPT 0x4A
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#define BCM2836_PV0_INTERRUPT 0x4D
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#define BCM2836_PV1_INTERRUPT 0x4E
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#define BCM2836_MBOX_INTERRUPT 0x41
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#define BCM2836_VCHIQ_INTERRUPT 0x42
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#define BCM2386_GPIO_INTERRUPT0 0x91
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#define BCM2386_GPIO_INTERRUPT1 0x92
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#define BCM2386_GPIO_INTERRUPT2 0x93
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#define BCM2386_GPIO_INTERRUPT3 0x94
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#define BCM2836_I2C1_INTERRUPT 0x95
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#define BCM2836_I2C2_INTERRUPT 0x95
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#define BCM2836_SPI0_INTERRUPT 0x96
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#define BCM2836_USB_INTERRUPT 0x69
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#define BCM2836_SDHOST_INTERRUPT 0x98
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#define BCM2836_MMCHS1_INTERRUPT 0x9E
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#define BCM2836_MINI_UART_INTERRUPT 0x7D
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#define BCM2836_PL011_UART_INTERRUPT 0x99
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#define GENET_INTERRUPT0 0xBD
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#define GENET_INTERRUPT1 0xBE
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#endif
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#endif // __ACPITABLES_H__
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