/** @file
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* Platform headers
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*
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* Copyright 2020 NXP
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* Copyright 2020 Puresoftware Ltd
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef LX2160ARDB_PLATFORM_H
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#define LX2160ARDB_PLATFORM_H
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#define EFI_ACPI_ARM_OEM_REVISION 0x00000000
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// Soc defines
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
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#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
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#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
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#define SVR_LX2160A 0x873600
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// PCLK
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#define DCFG_BASE 0x1E00000
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#define DCFG_LEN 0x1FFFF
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// Gic
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#define GIC_VERSION 3
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#define GICD_BASE 0x6000000
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#define GICI_BASE 0x6020000
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#define GICR_BASE 0x06200000
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#define GICR_LEN 0x200000
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#define GICC_BASE 0x0c0c0000
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#define GICH_BASE 0x0c0d0000
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#define GICV_BASE 0x0c0e0000
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// UART
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#define UART0_BASE 0x21C0000
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#define UART1_BASE 0x21D0000
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#define UART2_BASE 0x21E0000
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#define UART3_BASE 0x21F0000
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#define UART0_IT 64
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#define UART1_IT 65
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#define UART2_IT 104
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#define UART3_IT 105
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#define UART_LEN 0x10000
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#define SPCR_FLOW_CONTROL_NONE 0
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// Timer
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#define TIMER_BLOCK_COUNT 1
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#define TIMER_FRAME_COUNT 4
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#define TIMER_WATCHDOG_COUNT 1
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#define TIMER_BASE_ADDRESS 0x23E0000 // a.k.a CNTControlBase
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#define TIMER_READ_BASE_ADDRESS 0x23F0000 // a.k.a CNTReadBase
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#define TIMER_GT_BLOCK_0_ADDRESS 0x2890000 // a.k.a CNTCTLBase (Secure)
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#define TIMER_GT_BASE_0_ADDRESS 0x28A0000 // a.k.a CNTBase0
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#define TIMER_GT_BASE_1_ADDRESS 0x28B0000 // a.k.a CNTBase1
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#define TIMER_GT_BASE_2_ADDRESS 0x28C0000 // a.k.a CNTBase2
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#define TIMER_GT_BASE_3_ADDRESS 0x28D0000 // a.k.a CNTBase3
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#define TIMER_GT_BASE_0_EL0_ADDRESS 0x28E0000 // a.k.a CNTBase0EL0
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#define TIMER_GT_BASE_2_EL0_ADDRESS 0x28F0000 // a.k.a CNTBase2EL0
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#define TIMER_WDT0_REFRESH_BASE 0x2390000
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#define TIMER_WDT0_CONTROL_BASE 0x23A0000
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#define TIMER_SEC_IT 29
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#define TIMER_NON_SEC_IT 30
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#define TIMER_VIRT_IT 27
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#define TIMER_HYP_IT 26
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#define TIMER_FRAME0_IT 78
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#define TIMER_FRAME1_IT 79
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#define TIMER_FRAME2_IT 92
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#define TIMER_FRAME3_IT 93
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#define TIMER_WDT0_IT 91
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#define DEFAULT_PLAT_FREQ 700000000
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// Mcfg
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#define LX2160A_PCI_SEG0_CONFIG_BASE 0x9000000000
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#define LX2160A_PCI_SEG0 0x2
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#define LX2160A_PCI_SEG_BUSNUM_MIN 0x0
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#define LX2160A_PCI_SEG_BUSNUM_MAX 0xff
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#define LX2160A_PCI_SEG1_CONFIG_BASE 0xA000000000
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#define LX2160A_PCI_SEG1 0x4
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// Platform specific info needed by Configuration Manager
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#define OEM_ACPI_TABLES 1 // OEM defined DSDT
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#define CFG_MGR_TABLE_ID SIGNATURE_64 ('L','X','2','1','6','0',' ',' ')
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#define PLAT_PCI_SEG0_CONFIG_BASE LX2160A_PCI_SEG0_CONFIG_BASE
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#define PLAT_PCI_SEG0 LX2160A_PCI_SEG0
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#define PLAT_PCI_SEG_BUSNUM_MIN LX2160A_PCI_SEG_BUSNUM_MIN
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#define PLAT_PCI_SEG_BUSNUM_MAX LX2160A_PCI_SEG_BUSNUM_MAX
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#define PLAT_PCI_SEG1_CONFIG_BASE LX2160A_PCI_SEG1_CONFIG_BASE
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#define PLAT_PCI_SEG1 LX2160A_PCI_SEG1
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#define PLAT_GIC_VERSION GIC_VERSION
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#define PLAT_GICD_BASE GICD_BASE
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#define PLAT_GICI_BASE GICI_BASE
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#define PLAT_GICR_BASE GICR_BASE
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#define PLAT_GICR_LEN GICR_LEN
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#define PLAT_GICC_BASE GICC_BASE
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#define PLAT_GICH_BASE GICH_BASE
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#define PLAT_GICV_BASE GICV_BASE
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#define PLAT_CPU_COUNT 16
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#define PLAT_GTBLOCK_COUNT 1
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#define PLAT_GTFRAME_COUNT 4
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#define PLAT_PCI_CONFG_COUNT 2
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#define PLAT_WATCHDOG_COUNT 1
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#define PLAT_GIC_REDISTRIBUTOR_COUNT 1
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#define PLAT_GIC_ITS_COUNT 1
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/* GIC CPU Interface information
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GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficiency)
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*/
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#define PLAT_GIC_CPU_INTERFACE { \
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GICC_ENTRY (0, GET_MPID (0, 0), 23, 0x19, 0), \
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GICC_ENTRY (1, GET_MPID (0, 1), 23, 0x19, 0), \
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GICC_ENTRY (2, GET_MPID (1, 0), 23, 0x19, 0), \
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GICC_ENTRY (3, GET_MPID (1, 1), 23, 0x19, 0), \
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GICC_ENTRY (4, GET_MPID (2, 0), 23, 0x19, 0), \
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GICC_ENTRY (5, GET_MPID (2, 1), 23, 0x19, 0), \
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GICC_ENTRY (6, GET_MPID (3, 0), 23, 0x19, 0), \
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GICC_ENTRY (7, GET_MPID (3, 1), 23, 0x19, 0), \
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GICC_ENTRY (8, GET_MPID (4, 0), 23, 0x19, 0), \
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GICC_ENTRY (9, GET_MPID (4, 1), 23, 0x19, 0), \
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GICC_ENTRY (10, GET_MPID (5, 0), 23, 0x19, 0), \
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GICC_ENTRY (11, GET_MPID (5, 1), 23, 0x19, 0), \
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GICC_ENTRY (12, GET_MPID (6, 0), 23, 0x19, 0), \
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GICC_ENTRY (13, GET_MPID (6, 1), 23, 0x19, 0), \
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GICC_ENTRY (14, GET_MPID (7, 0), 23, 0x19, 0), \
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GICC_ENTRY (15, GET_MPID (7, 1), 23, 0x19, 0) \
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}
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// watchdogs
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#define PLAT_WATCHDOG_INFO \
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{ \
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TIMER_WDT0_CONTROL_BASE, \
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TIMER_WDT0_REFRESH_BASE, \
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TIMER_WDT0_IT, \
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SBSA_WATCHDOG_FLAGS \
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} \
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#define PLAT_TIMER_BLOCK_INFO \
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{ \
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{ \
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TIMER_GT_BLOCK_0_ADDRESS, \
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PLAT_GTFRAME_COUNT, \
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(CM_OBJECT_TOKEN)((UINT8*)&FslPlatformRepositoryInfo + \
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OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, GTBlock0TimerInfo)) \
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} \
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} \
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#define PLAT_TIMER_FRAME_INFO \
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{ \
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{ \
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0, /* UINT8 GTFrameNumber */ \
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TIMER_GT_BASE_0_ADDRESS, /* UINT64 CntBaseX */ \
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TIMER_GT_BASE_0_EL0_ADDRESS, /* UINT64 CntEL0BaseX */ \
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TIMER_FRAME0_IT, /* UINT32 GTxPhysicalTimerGSIV */ \
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GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
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TIMER_FRAME0_IT, /* UINT32 GTxVirtualTimerGSIV */ \
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GTDT_FRAME_FLAGS, /* UINT32 GTxVirtualTimerFlags */ \
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0 /* UINT32 GTxCommonFlags */ \
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}, /* Gtdt.Frames[0] */ \
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{ \
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1, /* UINT8 GTFrameNumber */ \
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TIMER_GT_BASE_1_ADDRESS, /* UINT64 CntBaseX */ \
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GT_BLOCK_FRAME_RES_BASE, /* UINT64 CntEL0BaseX */ \
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TIMER_FRAME1_IT, /* UINT32 GTxPhysicalTimerGSIV */ \
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GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
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0, /* UINT32 GTxVirtualTimerGSIV */ \
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0, /* UINT32 GTxVirtualTimerFlags */ \
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GTDT_FRAME_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
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}, /* Gtdt.Frames[1] */ \
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{ \
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2, /* UINT8 GTFrameNumber */ \
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TIMER_GT_BASE_2_ADDRESS, /* UINT64 CntBaseX */ \
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TIMER_GT_BASE_2_EL0_ADDRESS, /* UINT64 CntEL0BaseX */ \
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TIMER_FRAME2_IT, /* UINT32 GTxPhysicalTimerGSIV */ \
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GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
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0, /* UINT32 GTxVirtualTimerGSIV */ \
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0, /* UINT32 GTxVirtualTimerFlags */ \
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GTDT_FRAME_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
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},/* Gtdt.Frames[2] */ \
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{ \
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3, /* UINT8 GTFrameNumber */ \
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TIMER_GT_BASE_3_ADDRESS, /* UINT64 CntBaseX */ \
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GT_BLOCK_FRAME_RES_BASE, /* UINT64 CntEL0BaseX */ \
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TIMER_FRAME3_IT, /* UINT32 GTxPhysicalTimerGSIV */ \
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GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
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0, /* UINT32 GTxVirtualTimerGSIV */ \
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0, /* UINT32 GTxVirtualTimerFlags */ \
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GTDT_FRAME_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
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}, /* Gtdt.Frames[3] */ \
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} \
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#define PLAT_GIC_DISTRIBUTOR_INFO \
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{ \
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PLAT_GICD_BASE, /* UINT64 PhysicalBaseAddress */ \
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0, /* UINT32 SystemVectorBase */ \
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PLAT_GIC_VERSION /* UINT8 GicVersion */ \
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} \
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#define PLAT_GIC_REDISTRIBUTOR_INFO \
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{ \
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PLAT_GICR_BASE, /* UINT64 DiscoveryRangeBaseAddress */ \
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PLAT_GICR_LEN /* UINT32 DiscoveryRangeLength */ \
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} \
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#define PLAT_GIC_ITS_INFO \
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{ \
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0, /* UINT32 GIC ITS ID */ \
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PLAT_GICI_BASE, /* UINT64 The 64-bit physical address for ITS */ \
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0 /* UINT32 Populate the GIC ITS affinity in SRAT. */ \
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} \
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#define PLAT_MCFG_INFO \
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{ \
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{ \
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PLAT_PCI_SEG0_CONFIG_BASE, \
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PLAT_PCI_SEG0, \
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PLAT_PCI_SEG_BUSNUM_MIN, \
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PLAT_PCI_SEG_BUSNUM_MAX, \
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}, \
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{ \
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PLAT_PCI_SEG1_CONFIG_BASE, \
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PLAT_PCI_SEG1, \
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PLAT_PCI_SEG_BUSNUM_MIN, \
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PLAT_PCI_SEG_BUSNUM_MAX, \
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} \
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} \
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#define PLAT_SPCR_INFO \
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{ \
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UART0_BASE, \
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UART0_IT, \
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115200, \
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0, \
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EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART \
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} \
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#endif // LX2160ARDB_PLATFORM_H
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