/** NxpQoriqLsMem.c
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*
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* Board memory specific Library.
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*
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* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
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* Copyright 2017, 2019-2020 NXP
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Soc.h>
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
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/**
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Return the Virtual Memory Map of your platform
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This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
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@param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
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Virtual Memory mapping. This array must be ended by a zero-filled
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entry
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**/
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VOID
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ArmPlatformGetVirtualMemoryMap (
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IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
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)
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{
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UINTN Index;
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ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
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Index = 0;
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ASSERT (VirtualMemoryMap != NULL);
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VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
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EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
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if (VirtualMemoryTable == NULL) {
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return;
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}
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VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM0_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM0_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_DRAM0_SIZE;
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VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
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VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
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VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
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// CCSR Space
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VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// IFC region 1
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//
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// A-009241 : Unaligned write transactions to IFC may result in corruption of data
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// Affects : IFC
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// Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
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// writes on external IFC interface that can corrupt data on external flash.
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// Impact : Data corruption on external flash may happen in case of unaligned writes to
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// IFC memory space.
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// Workaround: Following are the workarounds:
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// For write transactions from core, IFC interface memories (including IFC SRAM)
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// should be configured as device type memory in MMU.
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// For write transactions from non-core masters (like system DMA), the address
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// should be 16 byte aligned and the data size should be multiple of 16 bytes.
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//
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VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC0_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_IFC0_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// QMAN SWP
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VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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// BMAN SWP
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VirtualMemoryTable[++Index].PhysicalBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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// IFC region 2
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VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC1_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_IFC1_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// PCIe1
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VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI0_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// PCIe2
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VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI1_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// PCIe3
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VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI2_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// QSPI region
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VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
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VirtualMemoryTable[Index].VirtualBase = LS1043A_QSPI_PHYS_ADDRESS;
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VirtualMemoryTable[Index].Length = LS1043A_QSPI_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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// End of Table
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VirtualMemoryTable[++Index].PhysicalBase = 0;
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VirtualMemoryTable[Index].VirtualBase = 0;
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VirtualMemoryTable[Index].Length = 0;
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VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
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*VirtualMemoryMap = VirtualMemoryTable;
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}
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