/** @file
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@copyright
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Copyright 2018 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiBoardInit.h"
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#include <ImonVrSvid.h>
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#include <Library/MemVrSvidMapLib.h>
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#include <Guid/PlatformInfo.h>
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#include <Library/UbaPcdUpdateLib.h>
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#include <Library/PcdLib.h>
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#include <UncoreCommonIncludes.h>
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#include <Ppi/DynamicSiLibraryPpi.h>
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#include <CpuAndRevisionDefines.h>
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#define GPIO_SKL_H_GPP_B20 0x01010014
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VOID TypeWilsonCityRPPlatformUpdateVrIdAddress (VOID);
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/**
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Update WilsonCity IMON SVID Information
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retval N/A
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**/
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VOID
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TypeWilsonCityRPPlatformUpdateImonAddress (
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VOID
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)
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{
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VCC_IMON *VccImon = NULL;
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UINTN Size = 0;
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Size = sizeof (VCC_IMON);
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VccImon = (VCC_IMON *) PcdGetPtr (PcdImonAddr);
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if (VccImon == NULL) {
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DEBUG ((EFI_D_ERROR, "UpdateImonAddress() - PcdImonAddr == NULL\n"));
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return;
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}
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VccImon->VrSvid[0] = PcdGet8 (PcdWilsonCitySvidVrP1V8);
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VccImon->VrSvid[1] = PcdGet8 (PcdWilsonCitySvidVrVccAna);
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VccImon->VrSvid[2] = IMON_ADDR_LIST_END; // End array with 0xFF
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PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon);
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}
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/**
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Update WilsonCity VR ID SVID Information
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retval N/A
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**/
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VOID
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TypeWilsonCityRPPlatformUpdateVrIdAddress (
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VOID
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)
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{
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MEM_SVID_MAP *MemSvidMap = NULL;
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UINTN Size = 0;
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Size = sizeof (MEM_SVID_MAP);
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MemSvidMap = (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap);
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if (MemSvidMap == NULL) {
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DEBUG ((EFI_D_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap == NULL\n"));
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return;
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}
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/*
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Map VR ID Address to Memory controller
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The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, and 0x16.
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Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (VR ID's 0x10 and 0x12).
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Those are typically shared such that MC0/MC2 share the same DDR VR (as they are on the same side of the CPU)
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and MC1/MC3 share the other. Depending on motherboard layout and other design constraints, this could change
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BIT 4 => 0 or 1, SVID BUS\Interface 0 or 1 respectively
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BIT 0:3 => SVID ADDRESS
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*/
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MemSvidMap->Socket[0].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
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MemSvidMap->Socket[0].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
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MemSvidMap->Socket[1].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
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MemSvidMap->Socket[1].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
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MemSvidMap->Socket[2].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
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MemSvidMap->Socket[2].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
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MemSvidMap->Socket[3].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
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MemSvidMap->Socket[3].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
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MemSvidMap->Socket[4].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
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MemSvidMap->Socket[4].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
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MemSvidMap->Socket[5].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
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MemSvidMap->Socket[5].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
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MemSvidMap->Socket[6].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
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MemSvidMap->Socket[6].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
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MemSvidMap->Socket[7].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
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MemSvidMap->Socket[7].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
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PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap);
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}
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EFI_STATUS
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TypeWilsonCityRPPlatformPcdUpdateCallback (
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VOID
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)
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{
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CHAR8 FamilyName[] = "Whitley";
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CHAR8 BoardName[] = "EPRP";
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UINT32 Data32;
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UINTN Size;
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UINTN PlatformFeatureFlag = 0;
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CHAR16 PlatformName[] = L"TypeWilsonCityRP";
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UINTN PlatformNameSize = 0;
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EFI_STATUS Status;
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//#Integer for BoardID, must match the SKU number and be unique.
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Status = PcdSet16S (PcdOemSkuBoardID , TypeWilsonCityRP);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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Status = PcdSet16S (PcdOemSkuBoardFamily , 0x30);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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// Number of Sockets on Board.
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Status = PcdSet32S (PcdOemSkuBoardSocketCount, 2);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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// Max channel and max DIMM
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Status = PcdSet32S (PcdOemSkuMaxChannel , 8);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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Status = PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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Status = PcdSetBoolS (PcdOemSkuDimmLayout, TRUE);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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//Update Onboard Video Controller PCI Ven_id, Dev_id
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Status = PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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Status = PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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//#
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//# Misc.
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//#
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//# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF
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Status = PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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//SDP Active Flag
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Status = PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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//# Zero terminated string to ID family
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Size = AsciiStrSize (FamilyName);
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Status = PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyName);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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//# Zero terminated string to Board Name
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Size = AsciiStrSize (BoardName);
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Status = PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardName);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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PlatformNameSize = sizeof (PlatformName);
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Status = PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)PlatformNameSize);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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Status = PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNameSize, PlatformName);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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//# FeaturesBasedOnPlatform
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Status = PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)PlatformFeatureFlag);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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//# Assert GPIO
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Data32 = 0;
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Status = PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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Status = PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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//# UplinkPortIndex
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Status = PcdSet8S (PcdOemSkuUplinkPortIndex, 5);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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DEBUG ((EFI_D_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\n"));
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Status = TypeWilsonCityRPPlatformUpdateAcpiTablePcds ();
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//# BMC Pcie Port Number
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PcdSet8S (PcdOemSkuBmcPciePortNumber, 5);
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ASSERT_EFI_ERROR(Status);
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//# Board Type Bit Mask
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PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4));
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ASSERT_EFI_ERROR(Status);
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//Update IMON Address
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TypeWilsonCityRPPlatformUpdateImonAddress ();
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return Status;
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}
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PLATFORM_PCD_UPDATE_TABLE TypeWilsonCityRPPcdUpdateTable =
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{
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PLATFORM_PCD_UPDATE_SIGNATURE,
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PLATFORM_PCD_UPDATE_VERSION,
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TypeWilsonCityRPPlatformPcdUpdateCallback
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};
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EFI_STATUS
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TypeWilsonCityRPInstallPcdData (
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IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
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)
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{
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EFI_STATUS Status;
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Status = UbaConfigPpi->AddData (
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UbaConfigPpi,
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&gPlatformPcdConfigDataGuid,
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&TypeWilsonCityRPPcdUpdateTable,
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sizeof(TypeWilsonCityRPPcdUpdateTable)
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);
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return Status;
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}
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