;------------------------------------------------------------------------------
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; @file PeiCoreEntry.nasm
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; Find and call SecStartup
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;
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; @copyright
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; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;------------------------------------------------------------------------------
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SECTION .text
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extern ASM_PFX(SecStartup)
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extern ASM_PFX(PlatformInit)
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global ASM_PFX(CallPeiCoreEntryPoint)
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ASM_PFX(CallPeiCoreEntryPoint):
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;
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; Obtain the hob list pointer
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;
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mov eax, [esp+4]
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;
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; Obtain the stack information
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; ECX: start of range
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; EDX: end of range
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;
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mov ecx, [esp+8]
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mov edx, [esp+0xC]
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;
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; Platform init
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;
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pushad
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push edx
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push ecx
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push eax
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call ASM_PFX(PlatformInit)
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pop eax
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pop eax
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pop eax
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popad
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;
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; Set stack top pointer
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;
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mov esp, edx
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;
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; Push the hob list pointer
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;
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push eax
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;
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; Save the value
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; ECX: start of range
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; EDX: end of range
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;
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mov ebp, esp
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push ecx
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push edx
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;
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; Push processor count to stack first, then BIST status (AP then BSP)
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;
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mov eax, 1
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cpuid
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shr ebx, 16
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and ebx, 0xFF
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cmp bl, 1
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jae PushProcessorCount
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;
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; Some processors report 0 logical processors. Effectively 0 = 1.
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; So we fix up the processor count
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;
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inc ebx
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PushProcessorCount:
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push ebx
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;
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; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
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; for all processor threads
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;
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xor ecx, ecx
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mov cl, bl
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PushBist:
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movd eax, mm0
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push eax
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loop PushBist
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; Save Time-Stamp Counter
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movd eax, mm5
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push eax
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movd eax, mm6
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push eax
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;
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; Pass entry point of the PEI core
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;
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mov edi, 0xFFFFFFE0
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push DWORD [edi]
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;
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; Pass BFV into the PEI Core
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;
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mov edi, 0xFFFFFFFC
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push DWORD [edi]
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;
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; Pass stack size into the PEI Core
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;
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mov ecx, [ebp - 4]
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mov edx, [ebp - 8]
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push ecx ; RamBase
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sub edx, ecx
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push edx ; RamSize
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;
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; Pass Control into the PEI Core
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;
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call ASM_PFX(SecStartup)
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