/** @file
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@copyright
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Copyright 2017 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SIO_REG_H_
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#define _SIO_REG_H_
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typedef struct {
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UINT8 Index;
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UINT8 Value;
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} SIO_INDEX_DATA;
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#define REG_LOGICAL_DEVICE 0x07
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#define ACTIVATE 0x30
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//
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// COM (Serial) Port Base address
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//
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#define SIO_BASE_COM1 0x3F8
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#define SIO_BASE_COM2 0x2F8
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#define BASE_ADDRESS_HIGH0 0x60
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#define BASE_ADDRESS_LOW0 0x61
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#define PRIMARY_INTERRUPT_SELECT 0x70
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#define INTERRUPT_TYPE 0x71
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//
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//ASPEED AST2500 register
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//
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#define ASPEED2500_SIO_INDEX_PORT 0x2E
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#define ASPEED2500_SIO_DATA_PORT (ASPEED2500_SIO_INDEX_PORT+1)
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#define ASPEED2500_SIO_UART1 0x02
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#define ASPEED2500_SIO_UART2 0x03
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#define ASPEED2500_SIO_SMI 0x0D
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#define ASPEED2500_SIO_MAILBOX 0x0E
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#define SCU7C 0x1e6e207c
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#define ASPEED2500_SIO_UNLOCK 0xA5
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#define ASPEED2500_SIO_LOCK 0xAA
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//
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// Port address for PILOT-IV
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//
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#define PILOTIV_CHIP_ID 0x03
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#define PILOTIV_SIO_INDEX_PORT 0x2E
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#define PILOTIV_SIO_DATA_PORT (PILOTIV_SIO_INDEX_PORT+1)
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#define PILOTIV_SIO_UNLOCK 0x5A
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#define PILOTIV_SIO_LOCK 0xA5
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#define PILOTIV_UNLOCK 0x5A
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#define PILOTIV_LOCK 0xA5
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#define PILOTIV_SIO_PSR 0x00
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#define PILOTIV_SIO_COM2 0x01
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#define PILOTIV_SIO_COM1 0x02
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#define PILOTIV_SIO_SWCP 0x03
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#define PILOTIV_SIO_GPIO 0x04
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#define PILOTIV_SIO_WDT 0x05
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#define PILOTIV_SIO_KCS3 0x08
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#define PILOTIV_SIO_KCS4 0x09
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#define PILOTIV_SIO_KCS5 0x0A
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#define PILOTIV_SIO_BT 0x0B
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#define PILOTIV_SIO_SMIC 0x0C
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#define PILOTIV_SIO_MAILBOX 0x0D
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#define PILOTIV_SIO_RTC 0x0E
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#define PILOTIV_SIO_SPI 0x0F
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#define PILOTIV_SIO_TAP 0x10
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//
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// Register for Pilot IV
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//
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#define PILOTIV_CHIP_ID_REG 0x20
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#define PILOTIV_LOGICAL_DEVICE REG_LOGICAL_DEVICE
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#define PILOTIV_ACTIVATE ACTIVATE
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#define PILOTIV_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
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#define PILOTIV_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
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#define PILOTIV_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1
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#define PILOTIV_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1
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#define PILOTIV_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
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//
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// Port address for PC8374
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//
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#define PC8374_CHIP_ID 0xF1
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#define PC8374_SIO_INDEX_PORT 0x02E
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#define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1)
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//
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// Logical device in PC8374
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//
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#define PC8374_SIO_FLOPPY 0x00
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#define PC8374_SIO_PARA 0x01
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#define PC8374_SIO_COM2 0x02
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#define PC8374_SIO_COM1 0x03
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#define PC8374_SIO_MOUSE 0x05
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#define PC8374_SIO_KYBD 0x06
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#define PC8374_SIO_GPIO 0x07
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//
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// Registers specific for PC8374
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//
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#define PC8374_CLOCK_SELECT 0x2D
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#define PC8374_CLOCK_CONFIG 0x29
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//
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// Registers for PC8374
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//
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#define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE
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#define PC8374_ACTIVATE ACTIVATE
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#define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
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#define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
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#define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
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#define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0
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#define PC8374_CHIP_ID_REG 0x20
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#define PC87427_SERVERIO_CNF2 0x22
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//
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// Port address for NCT5104D
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//
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#define NCT5104D_SIO_INDEX_PORT 0x4E
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#define NCT5104D_SIO_DATA_PORT (NCT5104D_SIO_INDEX_PORT+1)
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//
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// Registers for NCT5104D
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//
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#define NCT5104D_CHIP_ID_REG 0x20
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#define NCT5104D_CHIP_ID 0xC4
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#define NCT5104D_LOGICAL_DEVICE REG_LOGICAL_DEVICE
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#define NCT5104D_ACTIVATE ACTIVATE
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#define NCT5104D_SIO_UARTA 2
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#define NCT5104D_SIO_COM1 3
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#define NCT5104D_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
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#define NCT5104D_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
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#define NCT5104D_WAKEUP_ON_IRQ_EN 0x70
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#define NCT5104D_ENTER_THE_EXTENDED_FUNCTION_MODE 0x87
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#define NCT5104D_EXIT_THE_EXTENDED_FUNCTION_MODE 0xAA
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//
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// Port address for W83527
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//
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#define W83527_SIO_INDEX_PORT 0x02E
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#define W83527_SIO_DATA_PORT (W83527_SIO_INDEX_PORT+1)
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//
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// Logical device in W83527
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//
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#define W83527_SIO_KYBD 0x05
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#define W83527_SIO_WDTO 0x08
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#define W83527_SIO_GPIO 0x09
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#define W83527_SIO_ACPI 0x0A
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#define W83527_SIO_HWM 0x0B
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#define W83527_SIO_PCEI 0x0C
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//
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// Registers for W83527
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//
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#define W83527_EXT_MODE_START 0x87
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#define W83527_EXT_MODE_STOP 0xAA
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#define W83527_LOGICAL_DEVICE REG_LOGICAL_DEVICE
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#define W83527_ACTIVATE_REG 0x30
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#define W83527_ACTIVATE ACTIVATE
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#define W83527_CHIP_ID_REG 0x20
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#define W83527_CHIP_ID 0xB0
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#define W83527_CLOCK_REG 0x24
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#define W83527_KBC_BASE1_HI_ADDR_REG 0x60
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#define W83527_KBC_BASE1_LO_ADDR_REG 0x61
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#define W83527_KBC_BASE2_HI_ADDR_REG 0x62
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#define W83527_KBC_BASE2_LO_ADDR_REG 0x63
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#define W83527_KBC_BASE1_HI_ADDR 0x00
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#define W83527_KBC_BASE1_LO_ADDR 0x60
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#define W83527_KBC_BASE2_HI_ADDR 0x00
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#define W83527_KBC_BASE2_LO_ADDR 0x64
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#define W83527_KBC_KB_IRQ_REG 0x70
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#define W83527_KBC_KB_IRQ 0x01
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#define W83527_KBC_MS_IRQ_REG 0x72
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#define W83527_KBC_MS_IRQ 0x0C
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#define W83527_KBC_CFG_REG 0xF0
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#define W83527_KBC_CFG 0x83
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#define W83527_KBC_CLOCK 0x01
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#define W83527_EXT_MODE_START 0x87
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#define W83527_EXT_MODE_END 0xAA
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//
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// Select Clock for W83527, 0 / 1 for 24MHz / 48MHz
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//
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#define W83527_CLOCK_BIT 0x06
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#define W83527_CLOCK 0x01
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//
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// Initialize Key Board Controller
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//
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#define W83527_KeyBoard 1
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//
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// Pilot II Mailbox Data Register definitions
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//
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#define MBDAT00_OFFSET 0x00
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#define MBDAT01_OFFSET 0x01
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#define MBDAT02_OFFSET 0x02
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#define MBDAT03_OFFSET 0x03
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#define MBDAT04_OFFSET 0x04
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#define MBDAT05_OFFSET 0x05
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#define MBDAT06_OFFSET 0x06
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#define MBDAT07_OFFSET 0x07
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#define MBDAT08_OFFSET 0x08
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#define MBDAT09_OFFSET 0x09
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#define MBDAT10_OFFSET 0x0A
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#define MBDAT11_OFFSET 0x0B
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#define MBDAT12_OFFSET 0x0C
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#define MBDAT13_OFFSET 0x0D
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#define MBDAT14_OFFSET 0x0E
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#define MBDAT15_OFFSET 0x0F
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#define MBST0_OFFSET 0x10
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#define MBST1_OFFSET 0x11
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//
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// If both are there, use the default one
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//
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#define ASPEED_EXIST BIT4
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#define NCT5104D_EXIST BIT3
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#define W83527_EXIST BIT2
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#define PC8374_EXIST BIT1
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#define PILOTIV_EXIST BIT0
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#define DEFAULT_SIO PILOTIV_EXIST
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#define DEFAULT_KDB PC8374_EXIST
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#define IPMI_DEFAULT_SMM_IO_BASE 0xca2
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#define PILOTIV_SWC_BASE_ADDRESS 0xA00
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#define PILOTIV_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
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#define PILOTIV_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
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#define PILOTIV_GPE1_BLK_BASE_ADDRESS 0x0A86
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#define PILOTIV_KCS3_DATA_BASE_ADDRESS 0x0CA4
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#define PILOTIV_KCS3_CMD_BASE_ADDRESS 0x0CA5
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#define PILOTIV_KCS4_DATA_BASE_ADDRESS 0x0CA2
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#define PILOTIV_KCS4_CMD_BASE_ADDRESS 0x0CA3
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#define PILOTIV_MAILBOX_BASE_ADDRESS 0x0600
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#define PILOTIV_MAILBOX_MASK 0xFFE0
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#endif
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