/** @file
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Data format for Universal Data Structure
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@copyright
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Copyright 1999 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SETUP_VARIABLE_LBG_H_
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#define _SETUP_VARIABLE_LBG_H_
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// for PCH_RC_CONFIGURATION
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extern EFI_GUID gEfiPchSetupGuid;
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#define PCH_SETUP_NAME L"PchSetup"
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#include <PchLimits.h>
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#define HDAUDIO_FEATURES 3
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#define HDAUDIO_PP_MODULES 2
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#define SATA_MODE_AHCI 0
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#define SATA_MODE_RAID 1
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#define SATA_TEST_MODE_ENABLE 1
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/// sSATA max ports for Wellsburg
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#define PCH_MAX_SSATA_PORTS 6
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#pragma pack(1)
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typedef struct {
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UINT8 Dwr_Enable;
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UINT8 Dwr_Stall;
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UINT8 Dwr_BmcRootPort;
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UINT8 DwrEn_PMCGBL;
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UINT8 DwrEn_MEWDT;
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UINT8 DwrEn_IEWDT;
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UINT8 Dwr_MeResetPrepDone;
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UINT8 Dwr_IeResetPrepDone;
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//
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// PCH_DEVICE_ENABLES
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//
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UINT8 DeepSxMode;
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UINT8 Gp27WakeFromDeepSx;
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UINT8 GbeRegionInvalid;
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UINT8 LomLanSupported;
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UINT8 PchWakeOnLan;
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UINT8 PchSlpLanLowDc;
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UINT8 PchCrid;
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UINT8 PchRtcLock;
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UINT8 PchBiosLock;
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UINT8 PchAllUnLock;
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UINT8 PchThermalUnlock;
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UINT8 PchSerm;
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UINT8 Hpet;
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UINT8 PchPort80Route;
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UINT8 EnableClockSpreadSpec;
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UINT8 IchPort80Route;
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UINT8 PchSirqMode;
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//
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// Usb Config
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//
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UINT8 PchUsbManualMode;
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UINT8 PchGpioLockDown;
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UINT8 Usb3PinsTermination;
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UINT8 EnableUsb3Pin[10];
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UINT8 PchUsbHsPort[16];
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UINT8 PchUsbSsPort[10];
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UINT8 PchUsbPortDisable;
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UINT8 UsbSensorHub;
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UINT8 UsbSsicSupport[2];
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UINT8 XhciDisMSICapability;
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UINT8 PchUsbPerPortCtl;
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UINT8 PchUsb30Port[6];
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UINT8 UsbPrecondition;
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UINT8 XhciIdleL1;
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UINT8 Btcg;
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UINT8 PchUsbDegradeBar;
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//
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// XHCI OC Map
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//
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UINT8 XhciOcMapEnabled;
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//
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// xDCI Config
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//
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UINT8 PchXdciSupport;
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//
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// Sata CONFIG
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//
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UINT8 PchSata;
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//
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// Sata Interface Mode
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// 0 - IDE 1 - RAID 2 - AHCI
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//
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UINT8 SataInterfaceMode;
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UINT8 SataPort[PCH_MAX_SATA_PORTS];
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UINT8 SataHotPlug[PCH_MAX_SATA_PORTS];
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UINT8 SataMechanicalSw[PCH_MAX_SATA_PORTS];
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UINT8 SataSpinUp[PCH_MAX_SATA_PORTS];
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UINT8 SataExternal[PCH_MAX_SATA_PORTS];
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UINT8 SataType[PCH_MAX_SATA_PORTS];
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UINT8 SataRaidR0;
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UINT8 SataRaidR1;
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UINT8 SataRaidR10;
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UINT8 SataRaidR5;
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UINT8 SataRaidIrrt;
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UINT8 SataRaidOub;
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UINT8 SataHddlk;
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UINT8 SataLedl;
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UINT8 SataRaidIooe;
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UINT8 SataRaidSrt;
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UINT8 SataRaidLoadEfiDriver[PCH_MAX_SATA_CONTROLLERS];
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UINT8 SataRaidOromDelay;
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UINT8 SataAlternateId;
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UINT8 SataSalp;
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UINT8 SataTestMode;
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UINT8 PxDevSlp[PCH_MAX_SATA_PORTS];
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UINT8 EnableDitoConfig[PCH_MAX_SATA_PORTS];
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UINT16 DitoVal[PCH_MAX_SATA_PORTS];
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UINT8 DmVal[PCH_MAX_SATA_PORTS];
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UINT8 SataTopology[PCH_MAX_SATA_PORTS];
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//
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// sSata CONFIG
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//
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UINT8 PchsSata;
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//
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// Sata Interface Mode
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// 0 - IDE 1 - RAID 2 - AHCI
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//
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UINT8 sSataInterfaceMode;
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UINT8 sSataPort[PCH_MAX_SSATA_PORTS];
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UINT8 sSataHotPlug[PCH_MAX_SSATA_PORTS];
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UINT8 sSataSpinUp[PCH_MAX_SSATA_PORTS];
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UINT8 sSataExternal[PCH_MAX_SSATA_PORTS];
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UINT8 sPxDevSlp[PCH_MAX_SSATA_PORTS];
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UINT8 sSataType[PCH_MAX_SSATA_PORTS];
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UINT8 sSataRaidR0;
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UINT8 sSataRaidR1;
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UINT8 sSataRaidR10;
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UINT8 sSataRaidR5;
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UINT8 sSataRaidIrrt;
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UINT8 sSataRaidOub;
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UINT8 sSataHddlk;
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UINT8 sSataLedl;
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UINT8 sSataRaidIooe;
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UINT8 sSataRaidSrt;
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UINT8 sSataRaidOromDelay;
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UINT8 sSataAlternateId;
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UINT8 sSataSalp;
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UINT8 sSataTestMode;
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UINT8 sEnableDitoConfig[PCH_MAX_SSATA_PORTS];
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UINT8 sDmVal[PCH_MAX_SSATA_PORTS];
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UINT8 sDitoVal[PCH_MAX_SSATA_PORTS];
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UINT8 sSataTopology[PCH_MAX_SSATA_PORTS];
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//PCH THERMAL SENSOR
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UINT8 ThermalDeviceEnable;
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UINT8 PchCrossThrottling;
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UINT8 PchDmiExtSync;
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UINT8 PcieDmiExtSync;
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// AcpiDebug Setup Options
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UINT8 PciDelayOptimizationEcr;
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UINT8 PchPcieGlobalAspm;
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UINT8 PcieDmiStopAndScreamEnable;
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UINT8 DmiLinkDownHangBypass;
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UINT8 XTpmLen;
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UINT8 PcieRootPort8xhDecode;
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UINT8 Pcie8xhDecodePortIndex;
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UINT8 PcieRootPortPeerMemoryWriteEnable;
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UINT8 PcieComplianceTestMode;
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UINT8 PcieRootPortSBDE;
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UINT8 PcieSBDEPort;
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UINT8 RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR];
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UINT8 RstPcieStorageRemapPort[PCH_MAX_RST_PCIE_STORAGE_CR];
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UINT8 PcieRootPortFunctionSwapping;
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UINT8 PcieRootPortEn[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortAspm[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortURE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortFEE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortNFE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortCEE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortMaxPayLoadSize[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortAER[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieTopology[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieLaneCm[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieLaneCp[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieSwEqOverride;
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UINT8 PcieSwEqCoeffCm[PCH_PCIE_SWEQ_COEFFS_MAX];
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UINT8 PcieSwEqCoeffCp[PCH_PCIE_SWEQ_COEFFS_MAX];
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UINT8 PchPcieUX8MaxPayloadSize;
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UINT8 PchPcieUX16MaxPayloadSize;
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UINT8 PcieRootPortCompletionTimeout[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieClockGatingDisabled;
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UINT8 PcieUsbGlitchWa;
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UINT8 PcieRootPortPIE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortACS[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortEqPh3Method[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortMaxReadRequestSize;
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UINT8 PcieRootPortSFE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortSNE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortSCE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortPMCE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortHPE[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortSpeed[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PcieRootPortTHS[PCH_MAX_PCIE_ROOT_PORTS];
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//
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// PCI Bridge Resources
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//
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UINT8 PcieRootPortL1SubStates[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 MemoryThermalManagement;
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UINT8 ExttsViaTsOnBoard;
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UINT8 ExttsViaTsOnDimm;
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UINT8 FixupPlatformSpecificSoftstraps;
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//
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// SMBUS Configuration
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//
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UINT8 TestSmbusSpdWriteDisable;
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//
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// HD-Audio Configuration
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//
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UINT8 PchHdAudio;
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UINT8 PchHdAudioDsp;
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UINT8 PchHdAudioPme;
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UINT8 PchHdAudioIoBufferOwnership;
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UINT8 PchHdAudioIoBufferVoltage;
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UINT8 PchHdAudioCodecSelect;
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UINT8 PchHdAudioFeature[HDAUDIO_FEATURES];
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UINT8 PchHdAudioPostProcessingMod[HDAUDIO_PP_MODULES];
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UINT8 DfxHdaVcType;
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//
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// DMI Configuration
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//
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UINT8 TestDmiAspmCtrl;
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//
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//
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// PCIe LTR Configuration
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//
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UINT8 PchPcieLtrEnable[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PchPcieSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PchPcieSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PchPcieNonSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
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UINT16 PchPcieSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
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UINT16 PchPcieNonSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PchPcieForceLtrOverride[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PchSataLtrOverride;
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UINT8 PchSataLtrEnable;
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UINT16 PchSataSnoopLatencyOverrideValue;
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UINT8 PchSataSnoopLatencyOverrideMultiplier;
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UINT8 PchSataLtrConfigLock;
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UINT8 PchSSataLtrOverride;
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UINT16 PchSSataSnoopLatencyOverrideValue;
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UINT8 PchSSataSnoopLatencyOverrideMultiplier;
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UINT8 PchSSataLtrEnable;
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UINT8 PchSSataLtrConfigLock;
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UINT8 PchPcieUX16CompletionTimeout;
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UINT8 PchPcieUX8CompletionTimeout;
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//
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// Interrupt Configuration
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//
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UINT8 PchIoApic24119Entries;
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UINT8 ShutdownPolicySelect;
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//
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// DPTF SETUP items begin
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//
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UINT8 EnableDptf;
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UINT8 EnablePchDevice;
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//
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// Miscellaneous options
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//
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UINT8 SlpLanLowDc;
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UINT8 PchLanK1Off;
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UINT8 PchWakeOnWlan;
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UINT8 PchWakeOnWlanDeepSx;
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UINT8 StateAfterG3;
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UINT8 PciePllSsc;
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UINT8 FirmwareConfiguration;
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UINT8 DciEn;
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UINT8 PchDciAutoDetect;
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// Acpi.sd
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UINT8 CSNotifyEC;
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UINT8 EcLowPowerMode;
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//
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// TraceHub Setup Options
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//
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UINT8 PchTraceHubMode;
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UINT32 PchTraceHubMemReg0Size;
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UINT32 PchTraceHubMemReg1Size;
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UINT8 AetEnableMode;
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//
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// PCH P2SB hide and lock options
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//
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UINT8 PchP2sbDevReveal;
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UINT8 PchP2sbUnlock;
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//
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// PCH SPI hide and lock options
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//
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UINT8 ShowSpiController;
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UINT8 FlashLockDown;
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//
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// PCH PMC DFX options
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//
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UINT8 PmcReadDisable;
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//
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// ADR Configuration
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//
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UINT8 PchAdrEn;
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UINT8 AdrTimerEn;
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UINT8 AdrTimerVal;
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UINT8 AdrMultiplierVal;
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UINT8 AdrGpioSel;
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UINT8 AdrHostPartitionReset;
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UINT8 AdrSysPwrOk;
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UINT8 AdrOverClockingWdt;
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UINT8 AdrCpuThermalWdt;
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UINT8 AdrPmcParityError;
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//
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// Audio DSP Configuration
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//
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UINT8 PchAudioDsp;
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UINT8 PchAudioDspD3PowerGating;
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UINT8 PchAudioDspAcpiMode;
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UINT8 PchAudioDspBluetooth;
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UINT8 PchAudioDspAcpiInterruptMode;
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//
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// DFX Configuration
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//
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UINT8 PchEvaMrom0HookEnable;
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UINT8 PchEvaMrom1HookEnable;
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UINT8 TestMctpBroadcastCycle;
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UINT8 PchEvaLockDown;
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UINT8 PchTraceHubHide;
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} PCH_SETUP;
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#pragma pack()
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#endif
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