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/** @file
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Platform Hook Library instance for the UpXtreme Board
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <GpioPinsCnlLp.h>
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#include <Library/BaseLib.h>
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#include <Library/GpioLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PlatformHookLib.h>
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#include <PchAccess.h>
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#include <Uefi/UefiBaseType.h>
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#define LCR_OFFSET (FixedPcdGet32 (PcdSerialRegisterStride) * 0x03)
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STATIC GPIO_INIT_CONFIG mUartGpioTable[] = {
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{GPIO_CNL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
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{GPIO_CNL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
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};
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/**
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Retrieve the I/O or MMIO base address register for the PCI UART device.
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@retval The base address register of the UART device.
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**/
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STATIC
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UINTN
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GetSerialRegisterBase (
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VOID
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)
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{
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UINT64 PciAddress;
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UINT32 BaseAddressBuffer[2];
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UINT16 Cmd16;
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PciAddress = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2,
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PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2,
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0
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);
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Cmd16 = PciSegmentRead16 (PciAddress + PCI_VENDOR_ID_OFFSET);
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if (Cmd16 == 0xFFFF) {
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//
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// Device might be hidden, return the fixed serial register base address
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//
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return (UINTN) FixedPcdGet32 (PcdSerialRegisterBase);
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} else {
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if (PciSegmentRead32 (PciAddress + PCI_COMMAND_OFFSET) & EFI_PCI_COMMAND_MEMORY_SPACE) {
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BaseAddressBuffer[0] = PciSegmentRead32 (PciAddress + R_SERIAL_IO_CFG_BAR0_LOW) & B_SERIAL_IO_CFG_BAR0_LOW_BAR;
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BaseAddressBuffer[1] = 0;
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if ((PciSegmentRead32 (PciAddress + PCI_BASE_ADDRESSREG_OFFSET) & 0x6) == 0x4) {
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BaseAddressBuffer[1] = PciSegmentRead32 (PciAddress + R_SERIAL_IO_CFG_BAR0_HIGH);
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}
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return *((UINTN *) (&BaseAddressBuffer[0]));
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} else {
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return 0;
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}
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}
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}
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/**
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Performs platform specific initialization required for the CPU to access
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the hardware associated with a SerialPortLib instance. This function does
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not initialize the serial port hardware itself. Instead, it initializes
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hardware devices that are required for the CPU to access the serial port
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hardware. This function may be called more than once.
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@retval RETURN_SUCCESS The platform specific initialization succeeded.
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@retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
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**/
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RETURN_STATUS
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EFIAPI
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PlatformHookSerialPortInitialize (
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VOID
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)
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{
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UINT64 PciAddress;
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UINTN SerialRegisterBase;
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UINTN SerialRegisterBase1;
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PciAddress = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2,
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PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2,
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0
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);
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SerialRegisterBase = GetSerialRegisterBase ();
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if (SerialRegisterBase == 0 || SerialRegisterBase == (UINTN) ~0) {
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return RETURN_DEVICE_ERROR;
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}
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SerialRegisterBase1 = SerialRegisterBase + V_SERIAL_IO_CFG_BAR_SIZE;
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if (
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(MmioRead8 (SerialRegisterBase + LCR_OFFSET) & 0x3F) !=
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(FixedPcdGet8 (PcdSerialLineControl) & 0x3F)
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) {
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GpioConfigurePads ((sizeof (mUartGpioTable) / sizeof (GPIO_INIT_CONFIG)), mUartGpioTable);
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PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR0_LOW, (UINT32) SerialRegisterBase);
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PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR1_LOW, (UINT32) SerialRegisterBase1);
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if (sizeof (UINTN) == sizeof (UINT32)) {
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PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR0_HIGH, 0x0);
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PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR1_HIGH, 0x0);
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} else {
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PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR0_HIGH, (UINT32) RShiftU64 (SerialRegisterBase, 32));
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PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR1_HIGH, (UINT32) RShiftU64 (SerialRegisterBase1, 32));
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}
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PciSegmentWrite32 (PciAddress + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE);
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PciSegmentOr32 (PciAddress + R_SERIAL_IO_CFG_D0I3MAXDEVPG, BIT18 | BIT17 | BIT16);
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//
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// Get controller out of reset
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//
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MmioOr32 (SerialRegisterBase + R_SERIAL_IO_MEM_PPR_RESETS,
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B_SERIAL_IO_MEM_PPR_RESETS_FUNC | B_SERIAL_IO_MEM_PPR_RESETS_APB | B_SERIAL_IO_MEM_PPR_RESETS_IDMA);
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//
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// Program clock dividers for UARTs
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//
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MmioWrite32 (SerialRegisterBase + R_SERIAL_IO_MEM_PPR_CLK,
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(B_SERIAL_IO_MEM_PPR_CLK_UPDATE | (V_SERIAL_IO_MEM_PPR_CLK_N_DIV << 16) |
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(V_SERIAL_IO_MEM_PPR_CLK_M_DIV << 1) | B_SERIAL_IO_MEM_PPR_CLK_EN )
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);
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}
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return RETURN_SUCCESS;
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}
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