/** @file
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System Agent policy update.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiSaPolicyUpdate.h"
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#include <CpuRegs.h>
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#include <Library/CpuPlatformLib.h>
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#include <Guid/MemoryTypeInformation.h>
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#include <Guid/MemoryOverwriteControl.h>
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#include <Library/HobLib.h>
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#include <PchAccess.h>
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#include <SaAccess.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PeiSaPolicyLib.h>
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#include <Library/GpioLib.h>
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#include <GpioPinsSklH.h>
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/**
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Performs FSP SA PEI Policy initialization in pre-memory.
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@param[in][out] FspmUpd Pointer to FSP UPD Data.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
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EFI_STATUS
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EFIAPI
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PeiFspSaPolicyUpdatePreMem (
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IN OUT FSPM_UPD *FspmUpd
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)
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{
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VOID *Buffer;
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UINT8 BomId;
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FspmUpd->FspmConfig.SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0);
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FspmUpd->FspmConfig.SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1);
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FspmUpd->FspmConfig.SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2);
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FspmUpd->FspmConfig.SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3);
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FspmUpd->FspmConfig.MemorySpdDataLen = PcdGet16 (PcdMrcSpdDataSize);
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//
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// If SpdAddressTable are not all 0, it means DIMM slots implemented and
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// MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPolicyInitPreMem.
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//
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// If SpdAddressTable all 0, this is memory down design and hardcoded SpdData
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// should be applied to MemorySpdPtr*.
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//
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if ((PcdGet8 (PcdMrcSpdAddressTable0) == 0) && (PcdGet8 (PcdMrcSpdAddressTable1) == 0)
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&& (PcdGet8 (PcdMrcSpdAddressTable2) == 0) && (PcdGet8 (PcdMrcSpdAddressTable3) == 0)) {
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DEBUG ((DEBUG_INFO, "Using static SPD data for down memory.\n"));
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// BOMID [1:0]
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// 0: 16G A & B CH
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// 1: 8G A CH
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// 2: 8G A & B CH
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// 3: 4G A CH
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BomId = PcdGet8(PcdBoardBomId);
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if ((BomId & BIT0) == BIT0) {
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// Single Channel
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FspmUpd->FspmConfig.MemorySpdPtr00 = PcdGet32 (PcdMrcSpdData);
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FspmUpd->FspmConfig.MemorySpdPtr01 = 0;
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FspmUpd->FspmConfig.MemorySpdPtr10 = 0;
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FspmUpd->FspmConfig.MemorySpdPtr11 = 0;
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}else{
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// Dual Channel
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FspmUpd->FspmConfig.MemorySpdPtr00 = PcdGet32 (PcdMrcSpdData);
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FspmUpd->FspmConfig.MemorySpdPtr01 = 0;
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FspmUpd->FspmConfig.MemorySpdPtr10 = PcdGet32 (PcdMrcSpdData);
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FspmUpd->FspmConfig.MemorySpdPtr11 = 0;
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}
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// CopyMem (
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// (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr00,
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// (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
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// PcdGet16 (PcdMrcSpdDataSize)
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// );
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// CopyMem (
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// (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr10,
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// (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
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// PcdGet16 (PcdMrcSpdDataSize)
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// );
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}
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DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
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Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
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if (Buffer) {
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CopyMem ((VOID *) FspmUpd->FspmConfig.DqByteMapCh0, Buffer, sizeof (FspmUpd->FspmConfig.DqByteMapCh0));
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CopyMem (
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(VOID *) FspmUpd->FspmConfig.DqByteMapCh1,
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(UINT8 *) Buffer + sizeof (FspmUpd->FspmConfig.DqByteMapCh0),
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sizeof (FspmUpd->FspmConfig.DqByteMapCh1)
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);
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}
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Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
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if (Buffer) {
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CopyMem ((VOID *) FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, sizeof (FspmUpd->FspmConfig.DqsMapCpu2DramCh0));
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CopyMem (
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(VOID *) FspmUpd->FspmConfig.DqsMapCpu2DramCh1,
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(UINT8 *) Buffer + sizeof (FspmUpd->FspmConfig.DqsMapCpu2DramCh0),
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sizeof (FspmUpd->FspmConfig.DqsMapCpu2DramCh1)
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);
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}
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DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
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FspmUpd->FspmConfig.DqPinsInterleaved = (PcdGetBool (PcdMrcDqPinsInterleaved) ? 1 : 0);
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Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
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if (Buffer) {
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CopyMem ((VOID *) FspmUpd->FspmConfig.RcompResistor, Buffer, sizeof (FspmUpd->FspmConfig.RcompResistor));
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}
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Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
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if (Buffer) {
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CopyMem ((VOID *) FspmUpd->FspmConfig.RcompTarget, Buffer, sizeof (FspmUpd->FspmConfig.RcompTarget));
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}
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return EFI_SUCCESS;
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}
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