/*++
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Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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EfiRegTableLib.h
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Abstract:
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Definitions and macros for building register tables for chipset
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initialization..
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Components linking this lib must include PciRootBridgeIo and
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BootScriptSave protocols in their DPX.
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--*/
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#ifndef EFI_REG_TABLE_H
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#define EFI_REG_TABLE_H
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#include <PiDxe.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/UefiLib.h>
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#include <Protocol/PciRootBridgeIo.h>
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#define OPCODE_BASE(OpCode) ((UINT8)((OpCode) & 0xFF))
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#define OPCODE_FLAGS(OpCode) ((UINT8)(((OpCode) >> 8) & 0xFF))
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#define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))
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//
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// RegTable Base OpCodes
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//
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#define OP_TERMINATE_TABLE 0
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#define OP_MEM_WRITE 1
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#define OP_MEM_READ_MODIFY_WRITE 2
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#define OP_IO_WRITE 3
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#define OP_IO_READ_MODIFY_WRITE 4
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#define OP_PCI_WRITE 5
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#define OP_PCI_READ_MODIFY_WRITE 6
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#define OP_STALL 7
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//
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// RegTable OpCode Flags
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//
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#define OPCODE_FLAG_S3SAVE 1
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#define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }
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//
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// REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode
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// as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values
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//
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typedef struct {
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UINT32 OpCode;
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UINT32 PciAddress;
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UINT32 Data;
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} EFI_REG_TABLE_PCI_WRITE;
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#define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \
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{ \
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(UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
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(UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
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(UINT32) (Data), \
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(UINT32) (0) \
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}
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typedef struct {
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UINT32 OpCode;
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UINT32 MemAddress;
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UINT32 Data;
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} EFI_REG_TABLE_MEM_WRITE;
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typedef struct {
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UINT32 OpCode;
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UINT32 PciAddress;
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UINT32 OrMask;
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UINT32 AndMask;
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} EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;
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#define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag) \
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{ \
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(UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
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(UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
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(UINT32) (OrMask), \
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(UINT32) (AndMask) \
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}
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typedef struct {
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UINT32 OpCode;
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UINT32 MemAddress;
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UINT32 OrMask;
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UINT32 AndMask;
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} EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;
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#define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag) \
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{ \
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(UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
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(UINT32) (Address), \
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(UINT32) (OrMask), \
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(UINT32) (AndMask) \
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}
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typedef struct {
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UINT32 OpCode;
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UINT32 Field2;
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UINT32 Field3;
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UINT32 Field4;
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} EFI_REG_TABLE_GENERIC;
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typedef union {
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EFI_REG_TABLE_GENERIC Generic;
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EFI_REG_TABLE_PCI_WRITE PciWrite;
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EFI_REG_TABLE_PCI_READ_MODIFY_WRITE PciReadModifyWrite;
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EFI_REG_TABLE_MEM_READ_MODIFY_WRITE MemReadModifyWrite;
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} EFI_REG_TABLE;
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/**
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Processes register table assuming which may contain PCI, IO, MEM, and STALL
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entries.
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No parameter checking is done so the caller must be careful about omitting
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values for PciRootBridgeIo parameters. If the regtable does
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not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
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NULL).
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The RegTableEntry parameter is not checked, but is required.
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gBS is assumed to have been defined and is used when processing stalls.
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The function processes each entry sequentially until an OP_TERMINATE_TABLE
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entry is encountered.
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@param[in] RegTableEntry A pointer to the register table to process
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@param[in] PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
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when processing PCI table entries
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@retval Nothing.
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**/
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VOID
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ProcessRegTablePci (
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EFI_REG_TABLE * RegTableEntry,
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo
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);
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#endif
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