/** @file
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Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "TigerlakeURvpInit.h"
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#include "GpioTableTigerlakeUDdr4RvpPreMem.h"
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#include <PlatformBoardConfig.h>
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#include <Include/PlatformBoardId.h>
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#include <Library/GpioLib.h>
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/**
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Board Root Port Clock Info configuration init function for PEI pre-memory phase.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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RootPortClkInfoInit (
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IN UINT16 BoardId
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)
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{
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PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS];
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UINT32 Index;
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//
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// The default clock assignment will be FREE_RUNNING, which corresponds to PchClockUsageUnspecified
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// This is safe but power-consuming setting. If Platform code doesn't contain port-clock map for a given board,
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// the clocks will keep on running anyway, allowing PCIe devices to operate. Downside is that clocks will
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// continue to draw power. To prevent this, remember to provide port-clock map for every board.
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//
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for (Index = 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) {
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Clock[Index].PcieClock.ClkReqSupported = TRUE;
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Clock[Index].PcieClock.ClockUsage = FREE_RUNNING;
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}
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///
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/// Assign ClkReq signal to root port. (Base 0)
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/// For LP, Set 0 - 6
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/// For H, Set 0 - 15
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/// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port.
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///
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switch (BoardId) {
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// CLKREQ
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case BoardIdTglUDdr4:
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Clock[0].PcieClock.ClockUsage = PCIE_PEG;
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Clock[1].PcieClock.ClockUsage = PCIE_PCH + 2;
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Clock[2].PcieClock.ClockUsage = PCIE_PCH + 3;
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Clock[3].PcieClock.ClockUsage = PCIE_PCH + 8;
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Clock[4].PcieClock.ClockUsage = LAN_CLOCK;
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Clock[5].PcieClock.ClockUsage = PCIE_PCH + 7;
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Clock[6].PcieClock.ClockUsage = PCIE_PCH + 4;
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break;
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default:
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break;
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}
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PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
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PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
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PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
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PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
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PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
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PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
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PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
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PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
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PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
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PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
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PcdSet64S (PcdPcieClock10, Clock[10].Blob);
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PcdSet64S (PcdPcieClock11, Clock[11].Blob);
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PcdSet64S (PcdPcieClock12, Clock[12].Blob);
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PcdSet64S (PcdPcieClock13, Clock[13].Blob);
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PcdSet64S (PcdPcieClock14, Clock[14].Blob);
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PcdSet64S (PcdPcieClock15, Clock[15].Blob);
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return EFI_SUCCESS;
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}
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/**
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Board USB related configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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UsbConfigInit (
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IN UINT16 BoardId
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)
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{
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return EFI_SUCCESS;
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}
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/**
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Board GPIO Group Tier configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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GpioGroupTierInit (
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IN UINT16 BoardId
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)
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{
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return EFI_SUCCESS;
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}
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/**
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GPIO init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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GpioTablePreMemInit (
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IN UINT16 BoardId
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)
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{
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//
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// GPIO Table Init.
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//
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switch (BoardId) {
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case BoardIdTglUDdr4:
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PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTablePreMemTglUDdr4);
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PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTablePreMemTglUDdr4Size);
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break;
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default:
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break;
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}
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return EFI_SUCCESS;
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}
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/**
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PmConfig init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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PchPmConfigInit (
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IN UINT16 BoardId
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)
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{
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return EFI_SUCCESS;
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}
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