/** @file
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Implementation of Fsp PCH Policy Initialization.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PeiFspPolicyInitLib.h>
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#include <Ppi/SiPolicy.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/ConfigBlockLib.h>
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#include <Pins/GpioPinsVer2Lp.h>
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#include <TcssInfo.h>
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#include <TcssPeiConfig.h>
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#include <PolicyUpdateMacro.h>
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#include <PlatformBoardConfig.h>
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//
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// USB limits
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//
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#define PCH_MAX_USB2_PORTS 16
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#define PCH_MAX_USB3_PORTS 10
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//
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// TypeC port map GPIO pin
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//
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IOM_AUX_ORI_PAD_CONFIG mIomAuxNullTable[MAX_IOM_AUX_BIAS_COUNT] = {
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// Pull UP GPIO Pin, Pull Down GPIO pin
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{0, 0}, // Port 0
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{0, 0}, // Port 1
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{0, 0}, // Port 2
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{0, 0}, // Port 3
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};
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VOID
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UpdatePcieClockInfo (
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PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig,
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IN FSPM_UPD *FspmUpd,
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UINTN Index,
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UINT64 Data
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)
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{
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PCD64_BLOB Pcd64;
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Pcd64.Blob = Data;
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DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
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UPDATE_POLICY (FspmUpd->FspmConfig.PcieClkSrcUsage[Index], PcieRpPreMemConfig->PcieClock[Index].Usage, (UINT8)Pcd64.PcieClock.ClockUsage);
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UPDATE_POLICY (FspmUpd->FspmConfig.PcieClkSrcClkReq[Index], PcieRpPreMemConfig->PcieClock[Index].ClkReq, Pcd64.PcieClock.ClkReqSupported ? (UINT8)Index : 0xFF);
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}
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/**
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Performs FSP PCH PEI Policy pre mem initialization.
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@param[in][out] FspmUpd Pointer to FSP UPD Data.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
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EFI_STATUS
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EFIAPI
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PeiFspPchPolicyInitPreMem (
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IN OUT FSPM_UPD *FspmUpd
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)
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{
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UINTN Index;
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PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
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HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig;
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#if FixedPcdGet8(PcdFspModeSelection) == 0
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SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
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EFI_STATUS Status;
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//
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// Locate PchPreMemPolicyPpi
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//
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SiPreMemPolicy = NULL;
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PcieRpPreMemConfig = NULL;
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HdaPreMemConfig = NULL;
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Status = PeiServicesLocatePpi (
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&gSiPreMemPolicyPpiGuid,
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0,
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NULL,
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(VOID **) &SiPreMemPolicy
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);
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if (EFI_ERROR (Status)) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfigGuid, (VOID *) &HdaPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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#else
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PcieRpPreMemConfig = NULL;
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HdaPreMemConfig = NULL;
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#endif
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64 (PcdPcieClock0));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64 (PcdPcieClock1));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64 (PcdPcieClock2));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64 (PcdPcieClock3));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64 (PcdPcieClock4));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64 (PcdPcieClock5));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64 (PcdPcieClock6));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64 (PcdPcieClock7));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64 (PcdPcieClock8));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64 (PcdPcieClock9));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64 (PcdPcieClock10));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64 (PcdPcieClock11));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64 (PcdPcieClock12));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64 (PcdPcieClock13));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64 (PcdPcieClock14));
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UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64 (PcdPcieClock15));
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//
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// Update HDA policies
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//
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UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaIDispLinkTmode, HdaPreMemConfig->IDispLinkTmode, 0);
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UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaSdiEnable[0], HdaPreMemConfig->AudioLinkHda.SdiEnable[0], FALSE);
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for (Index = 0; Index < GetPchHdaMaxDmicLinkNum (); Index++) {
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UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaAudioLinkDmicClockSelect[Index], HdaPreMemConfig->AudioLinkDmic[Index].DmicClockSelect, 0);
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}
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DEBUG((DEBUG_INFO | DEBUG_INIT, "UpdatePeiPchPolicyPreMem\n"));
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return EFI_SUCCESS;
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}
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/**
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This function updates USB Policy per port OC Pin number
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@param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
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@param[in] PortIndex USB Port index
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@param[in] Pin OverCurrent pin number
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**/
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VOID
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UpdateUsb20OverCurrentPolicy (
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IN OUT FSPS_UPD *FspsUpd,
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IN USB_CONFIG *UsbConfig,
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IN UINT8 PortIndex,
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UINT8 Pin
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)
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{
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if (PortIndex < MAX_USB2_PORTS && ((Pin < USB_OC_MAX_PINS) || (Pin == USB_OC_SKIP))) {
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UPDATE_POLICY (
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FspsUpd->FspsConfig.Usb2OverCurrentPin[PortIndex],
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UsbConfig->PortUsb20[PortIndex].OverCurrentPin,
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Pin
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);
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} else {
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if (PortIndex >= MAX_USB2_PORTS) {
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DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number %d is not a valid USB2 port number\n", PortIndex));
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} else {
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DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurrent pin specified USB2 port %d\n", PortIndex));
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}
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}
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}
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/**
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This function updates USB Policy per port OC Pin number
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@param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
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@param[in] PortIndex USB Port index
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@param[in] Pin OverCurrent pin number
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**/
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VOID
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UpdateUsb30OverCurrentPolicy (
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IN OUT FSPS_UPD *FspsUpd,
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IN USB_CONFIG *UsbConfig,
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IN UINT8 PortIndex,
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UINT8 Pin
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)
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{
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if (PortIndex < MAX_USB3_PORTS && ((Pin < USB_OC_MAX_PINS) || (Pin == USB_OC_SKIP))) {
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UPDATE_POLICY (
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FspsUpd->FspsConfig.Usb3OverCurrentPin[PortIndex],
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UsbConfig->PortUsb30[PortIndex].OverCurrentPin,
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Pin
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);
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} else {
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if (PortIndex >= MAX_USB2_PORTS) {
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DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number %d is not a valid USB3 port number\n", PortIndex));
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} else {
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DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurrent pin specified USB3 port %d\n", PortIndex));
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}
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}
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}
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/**
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This function performs PCH USB Platform Policy initialization
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@param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
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@param[in] PchSetup Pointer to PCH_SETUP data buffer
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**/
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VOID
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UpdatePchUsbConfig (
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IN OUT FSPS_UPD *FspsUpd,
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IN OUT USB_CONFIG *UsbConfig
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)
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{
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UINTN PortIndex;
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UPDATE_POLICY (FspsUpd->FspsConfig.PchUsbOverCurrentEnable, UsbConfig->OverCurrentEnable, TRUE);
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for (PortIndex = 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortIndex++) {
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UPDATE_POLICY (FspsUpd->FspsConfig.PortUsb20Enable[PortIndex], UsbConfig->PortUsb20[PortIndex].Enable, TRUE);
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}
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for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
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UPDATE_POLICY (FspsUpd->FspsConfig.PortUsb30Enable[PortIndex], UsbConfig->PortUsb30[PortIndex].Enable, TRUE);
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}
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UPDATE_POLICY (FspsUpd->FspsConfig.XdciEnable, UsbConfig->XdciConfig.Enable, FALSE);
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//
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// Platform Board programming per the layout of each port.
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//
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 0, PcdGet8 (PcdUsb20OverCurrentPinPort0));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 1, PcdGet8 (PcdUsb20OverCurrentPinPort1));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 2, PcdGet8 (PcdUsb20OverCurrentPinPort2));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 3, PcdGet8 (PcdUsb20OverCurrentPinPort3));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 4, PcdGet8 (PcdUsb20OverCurrentPinPort4));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 5, PcdGet8 (PcdUsb20OverCurrentPinPort5));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 6, PcdGet8 (PcdUsb20OverCurrentPinPort6));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 7, PcdGet8 (PcdUsb20OverCurrentPinPort7));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 8, PcdGet8 (PcdUsb20OverCurrentPinPort8));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 9, PcdGet8 (PcdUsb20OverCurrentPinPort9));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,10, PcdGet8 (PcdUsb20OverCurrentPinPort10));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,11, PcdGet8 (PcdUsb20OverCurrentPinPort11));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,12, PcdGet8 (PcdUsb20OverCurrentPinPort12));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,13, PcdGet8 (PcdUsb20OverCurrentPinPort13));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,14, PcdGet8 (PcdUsb20OverCurrentPinPort14));
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UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,15, PcdGet8 (PcdUsb20OverCurrentPinPort15));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 0, PcdGet8 (PcdUsb30OverCurrentPinPort0));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 1, PcdGet8 (PcdUsb30OverCurrentPinPort1));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 2, PcdGet8 (PcdUsb30OverCurrentPinPort2));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 3, PcdGet8 (PcdUsb30OverCurrentPinPort3));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 4, PcdGet8 (PcdUsb30OverCurrentPinPort4));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 5, PcdGet8 (PcdUsb30OverCurrentPinPort5));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 6, PcdGet8 (PcdUsb30OverCurrentPinPort6));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 7, PcdGet8 (PcdUsb30OverCurrentPinPort7));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 8, PcdGet8 (PcdUsb30OverCurrentPinPort8));
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UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 9, PcdGet8 (PcdUsb30OverCurrentPinPort9));
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}
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/**
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Update CNVi config
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@param[in] SiPolicy Pointer to SI_POLICY_PPI
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@param[in] FspsUpd Pointer to FspsUpd structure
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@param[in] PchSetup Pointer to PCH_SETUP buffer
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**/
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STATIC
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VOID
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UpdateCnviConfig (
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IN OUT FSPS_UPD *FspsUpd,
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IN OUT CNVI_CONFIG *CnviConfig
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)
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{
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UPDATE_POLICY (FspsUpd->FspsConfig.CnviMode, CnviConfig->Mode, CnviModeDisabled);
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UPDATE_POLICY (FspsUpd->FspsConfig.CnviBtCore, CnviConfig->BtCore, FALSE);
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UPDATE_POLICY (FspsUpd->FspsConfig.CnviBtAudioOffload, CnviConfig->BtAudioOffload, 0);
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}
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/**
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Performs FSP PCH PEI Policy initialization.
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@param[in][out] FspsUpd Pointer to FSP UPD Data.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
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EFI_STATUS
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EFIAPI
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PeiFspPchPolicyInit (
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IN OUT FSPS_UPD *FspsUpd
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)
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{
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UINTN Index;
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SATA_CONFIG *SataConfig;
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USB_CONFIG *UsbConfig;
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TCSS_PEI_CONFIG *TcssConfig;
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SERIAL_IO_CONFIG *SerialIoConfig;
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CNVI_CONFIG *CnviConfig;
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#if FixedPcdGet8(PcdFspModeSelection) == 0
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SI_POLICY_PPI *SiPolicy;
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EFI_STATUS Status;
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#endif
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DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n"));
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SataConfig = NULL;
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UsbConfig = NULL;
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TcssConfig = NULL;
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SerialIoConfig = NULL;
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CnviConfig = NULL;
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#if FixedPcdGet8(PcdFspModeSelection) == 0
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//
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// Locate SiPolicyPpi
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//
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SiPolicy = NULL;
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Status = PeiServicesLocatePpi (
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&gSiPolicyPpiGuid,
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0,
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NULL,
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(VOID **) &SiPolicy
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);
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if (EFI_ERROR (Status)) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gTcssPeiConfigGuid, (VOID *) &TcssConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *) &CnviConfig);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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#endif
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//
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// Update Sata Policies
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//
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UPDATE_POLICY (FspsUpd->FspsConfig.SataEnable, SataConfig->Enable, TRUE);
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UPDATE_POLICY (FspsUpd->FspsConfig.SataMode, SataConfig->SataMode, SataModeAhci);
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for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index++) {
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UPDATE_POLICY (FspsUpd->FspsConfig.SataPortsEnable[Index], SataConfig->PortSettings[Index].Enable, TRUE);
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}
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//
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// Update Pch Usb Config
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//
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UpdatePchUsbConfig (FspsUpd, UsbConfig);
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//
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// I2C
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//
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for (Index = 0; Index < 8; Index++) {
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UPDATE_POLICY (FspsUpd->FspsConfig.SerialIoI2cMode[Index], SerialIoConfig->I2cDeviceConfig[Index].Mode, 0);
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UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[Index], SerialIoConfig->I2cDeviceConfig[Index].PadTermination, 0);
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}
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UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cSdaPinMux[4], SerialIoConfig->I2cDeviceConfig[4].PinMux.Sda, GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_H8);
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UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cSclPinMux[4], SerialIoConfig->I2cDeviceConfig[4].PinMux.Scl, GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_H9);
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//
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// Type C
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//
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for (Index = 0; Index < MAX_IOM_AUX_BIAS_COUNT; Index++) {
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UPDATE_POLICY (FspsUpd->FspsConfig.IomTypeCPortPadCfg[(Index * 2)], TcssConfig->IomConfig.IomAuxPortPad[Index].GpioPullN, mIomAuxNullTable[Index].GpioPullN);
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UPDATE_POLICY (FspsUpd->FspsConfig.IomTypeCPortPadCfg[(Index * 2) + 1], TcssConfig->IomConfig.IomAuxPortPad[Index].GpioPullP, mIomAuxNullTable[Index].GpioPullP);
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}
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//
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// Cnvi
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//
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UpdateCnviConfig (FspsUpd, CnviConfig);
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return EFI_SUCCESS;
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}
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