/** @file
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// The package level header files this module uses
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//
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#include <PiPei.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/PeimEntryPoint.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/ResourcePublicationLib.h>
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#include <Library/CmosAccessLib.h>
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#include <Guid/MemoryTypeInformation.h>
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#include <Ppi/MasterBootMode.h>
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#include <IndustryStandard/Pci22.h>
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#include <SimicsPlatforms.h>
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#include "Platform.h"
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EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
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{ EfiACPIMemoryNVS, 0x004 },
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{ EfiACPIReclaimMemory, 0x008 },
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{ EfiReservedMemoryType, 0x004 },
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{ EfiRuntimeServicesData, 0x024 },
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{ EfiRuntimeServicesCode, 0x030 },
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{ EfiBootServicesCode, 0x180 },
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{ EfiBootServicesData, 0xF00 },
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{ EfiMaxMemoryType, 0x000 }
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};
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EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gEfiPeiMasterBootModePpiGuid,
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NULL
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}
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};
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UINT16 mHostBridgeDevId;
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EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
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BOOLEAN mS3Supported = FALSE;
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UINT32 mMaxCpuCount;
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_MAPPED_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize,
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BOOLEAN Cacheable
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_RESERVED,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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(Cacheable ?
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
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0
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) |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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AddUntestedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddUntestedMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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AddFlashDeviceRange (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_FIRMWARE_DEVICE,
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(EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
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MemoryBase,
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MemorySize
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);
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BuildMemoryAllocationHob (
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MemoryBase,
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MemorySize,
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EfiMemoryMappedIO
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);
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}
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VOID
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MemMapInitialization (
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VOID
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)
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{
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UINT64 PciIoBase;
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UINT64 PciIoSize;
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UINT32 TopOfLowRam;
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UINT64 PciExBarBase;
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UINT32 PciBase;
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UINT32 PciSize;
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PciIoBase = 0xC000;
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PciIoSize = 0x4000;
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//
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// Create Memory Type Information HOB
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//
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BuildGuidDataHob (
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&gEfiMemoryTypeInformationGuid,
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mDefaultMemoryTypeInformation,
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sizeof(mDefaultMemoryTypeInformation)
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);
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//
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// Video memory + Legacy BIOS region
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//
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AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
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TopOfLowRam = GetSystemMemorySizeBelow4gb ();
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PciExBarBase = 0;
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if (mHostBridgeDevId == INTEL_ICH10_DEVICE_ID) {
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//
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// The MMCONFIG area is expected to fall between the top of low RAM and
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// the base of the 32-bit PCI host aperture.
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//
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PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
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ASSERT (TopOfLowRam <= PciExBarBase);
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ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
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PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
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} else {
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PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
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}
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//
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// address purpose size
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// ------------ -------- -------------------------
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// 0x00000000 TopOfLowRam 0xDF000000
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// 0xDF000000 Tseg+UMA 0x01000000
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// 0xE0000000 PciExBarBase 0x10000000
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// 0xF0000000 PciBase 0x0C000000
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// -------------------------------------------------
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// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
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// 0xFC000000 gap 44 MB
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// 0xFEC00000 IO-APIC 4 KB
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// 0xFEC01000 gap 1020 KB
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// 0xFED00000 HPET 1 KB
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// 0xFED00400 gap 111 KB
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// 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
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// 0xFED20000 gap 896 KB
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// 0xFEE00000 LAPIC 1 MB
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//
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PciSize = 0xFC000000 - PciBase;
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AddIoMemoryBaseSizeHob (PciBase, PciSize);
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PcdSet64S (PcdPciMmio32Base, PciBase);
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PcdSet64S (PcdPciMmio32Size, PciSize);
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AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
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AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
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if (mHostBridgeDevId == INTEL_ICH10_DEVICE_ID) {
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AddIoMemoryBaseSizeHob (ICH10_ROOT_COMPLEX_BASE, SIZE_16KB);
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//
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// Note: there should be an
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//
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// AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
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// BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB, EfiMemoryMappedIO);
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//
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// call below, just like the one above for RCBA. However, Linux insists
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// that the MMCONFIG area be marked in the E820 or UEFI memory map as
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// "reserved memory" -- Linux does not content itself with a simple gap
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// in the memory map wherever the MCFG ACPI table points to.
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//
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// This appears to be a safety measure. The PCI Firmware Specification
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// (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
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// *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
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// [...]". (Emphasis added here.)
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//
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// Normally we add memory resource descriptor HOBs in
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// QemuInitializeRam(), and pre-allocate from those with memory
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// allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
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// is most definitely not RAM; so, as an exception, cover it with
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// uncacheable reserved memory right here.
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//
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AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
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BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
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EfiReservedMemoryType);
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}
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AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
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// Add PCI IO Port space available for PCI resource allocations.
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//
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BuildResourceDescriptorHob (
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EFI_RESOURCE_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
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PciIoBase,
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PciIoSize
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);
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PcdSet64S (PcdPciIoBase, PciIoBase);
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PcdSet64S (PcdPciIoSize, PciIoSize);
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//
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// Add flash range.
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//
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AddFlashDeviceRange (PcdGet32(PcdFlashAreaBaseAddress), PcdGet32(PcdFlashAreaSize));
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//
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// Video memory / ABSEG
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//
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AddIoMemoryBaseSizeHob (0x0A0000, 0x20000);
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//
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// Legacy BIOS region.
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//
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AddReservedMemoryBaseSizeHob (0xC0000, 0x40000, TRUE);
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}
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VOID
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MiscInitialization (
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VOID
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)
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{
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UINTN PmCmd;
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UINTN Pmba;
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UINT32 PmbaAndVal;
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UINT32 PmbaOrVal;
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UINTN AcpiCtlReg;
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UINT8 AcpiEnBit;
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//
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// Disable A20 Mask
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//
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IoOr8 (0x92, BIT1);
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//
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// Build the CPU HOB with guest RAM size dependent address width and 16-bits
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// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
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// S3 resume as well, so we build it unconditionally.)
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//
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BuildCpuHob (mPhysMemAddressWidth, 16);
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//
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// Determine platform type and save Host Bridge DID to PCD
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//
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switch (mHostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
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PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
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PmbaOrVal = PIIX4_PMBA_VALUE;
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AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
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AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
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break;
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case INTEL_ICH10_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_ICH10 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_ICH10 (ICH10_PMBASE);
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PmbaAndVal = ~(UINT32)ICH10_PMBASE_MASK;
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PmbaOrVal = ICH10_PMBASE_VALUE;
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AcpiCtlReg = POWER_MGMT_REGISTER_ICH10 (ICH10_ACPI_CNTL);
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AcpiEnBit = ICH10_ACPI_CNTL_ACPI_EN;
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break;
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default:
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DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__, mHostBridgeDevId));
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ASSERT (FALSE);
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return;
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}
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PcdSet16S (PcdSimicsX58HostBridgePciDevId, mHostBridgeDevId);
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//
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// If the appropriate IOspace enable bit is set, assume the ACPI PMBA
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// has been configured and skip the setup here.
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// This matches the logic in AcpiTimerLibConstructor ().
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//
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if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
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//
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// The PEI phase should be exited with fully accessibe ACPI PM IO space:
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// 1. set PMBA
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//
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PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
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//
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// 2. set PCICMD/IOSE
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//
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PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
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//
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// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
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//
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PciOr8 (AcpiCtlReg, AcpiEnBit);
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}
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if (mHostBridgeDevId == INTEL_ICH10_DEVICE_ID) {
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//
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// Set Root Complex Register Block BAR
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//
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PciWrite32 (
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POWER_MGMT_REGISTER_ICH10 (ICH10_RCBA),
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ICH10_ROOT_COMPLEX_BASE | ICH10_RCBA_EN
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);
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}
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//
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// Set the PM I/O base address to 0x400
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//
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PciAndThenOr32 (
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PCI_LIB_ADDRESS (
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0,
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31,
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0,
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0x40
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),
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(UINT32) ~0xfc0, ICH10_PMBASE_VALUE
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);
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//
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// Enable AHCI and all ports on the SATA controller.
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//
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// Address MAP Reg, setting AHCI mode
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//
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PciOr16 (PCI_LIB_ADDRESS (0, 31, 2, 0x90), 0x0060);
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//
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//Enabling Ports 0-5
|
//
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PciOr16 (PCI_LIB_ADDRESS (0, 31, 2, 0x92), 0x003F);
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//
|
//Disabling Sata Controller 2, bit 25 = 1, bit 0 = 1
|
//
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MmioWrite32(0xFED1F418, 0x02000001);
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//
|
//Enable HPET at FED0_0000h ? FED0_03FFh
|
//
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MmioWrite8(ICH10_ROOT_COMPLEX_BASE + 0x3404, 0x80);
|
//
|
//Config and enable APIC
|
//
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MmioWrite32(0xFEC00000 + 0X0, 0);
|
MmioWrite32(0xFEC00000 + 0X10, PcdGet8(PcdIoApicId)<<24);
|
MmioWrite8(ICH10_ROOT_COMPLEX_BASE + 0x31FF, 0x01);
|
}
|
|
|
VOID
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BootModeInitialization (
|
VOID
|
)
|
{
|
EFI_STATUS Status;
|
|
DEBUG((EFI_D_INFO, "modeValue = %x\n", IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12)));
|
if (IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12) == 0x5) {
|
mBootMode = BOOT_ON_S3_RESUME;
|
}
|
|
Status = PeiServicesSetBootMode (mBootMode);
|
ASSERT_EFI_ERROR (Status);
|
|
Status = PeiServicesInstallPpi (mPpiBootMode);
|
ASSERT_EFI_ERROR (Status);
|
}
|
|
|
VOID
|
ReserveEmuVariableNvStore (
|
)
|
{
|
EFI_PHYSICAL_ADDRESS VariableStore;
|
|
//
|
// Allocate storage for NV variables early on so it will be
|
// at a consistent address. Since VM memory is preserved
|
// across reboots, this allows the NV variable storage to survive
|
// a VM reboot.
|
//
|
VariableStore =
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(EFI_PHYSICAL_ADDRESS)(UINTN)
|
AllocateRuntimePages (
|
EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
|
);
|
DEBUG ((EFI_D_INFO,
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"Reserved variable store memory: 0x%lX; size: %dkb\n",
|
VariableStore,
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(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
|
));
|
PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
|
}
|
|
|
VOID
|
SimicsVersionCheck(
|
VOID
|
)
|
{
|
|
UINTN PciAddrPtr;
|
UINT8 CapOffset;
|
STATIC CHAR8 SimicsStr[0x100];
|
UINTN i;
|
UINT32 MajorVersion;
|
UINT32 MinorVersion;
|
UINT32 ModelNumber;
|
|
PciAddrPtr = PCI_LIB_ADDRESS(0, SIMICS_SIDEBANDPCI_DEV, SIMICS_SIDEBANDPCI_FUNC, 0);
|
CapOffset = PciRead8(PciAddrPtr + PCI_CAPBILITY_POINTER_OFFSET);
|
if (CapOffset != 0xFF) {
|
ModelNumber = PciRead32(PciAddrPtr + CapOffset + 4);
|
MajorVersion = PciRead32(PciAddrPtr + CapOffset + 8);
|
MinorVersion = PciRead32(PciAddrPtr + CapOffset + 0xc);
|
for (i = 0; i < 0x80; i++) {
|
SimicsStr[i] = PciRead8(PciAddrPtr + CapOffset + 0x10 + i);
|
}
|
DEBUG((EFI_D_INFO, "=============SIMICS Version info=============\n"));
|
DEBUG((EFI_D_INFO, "Model number = %d\n", ModelNumber));
|
DEBUG((EFI_D_INFO, "Major version = %d\n", MajorVersion));
|
DEBUG((EFI_D_INFO, "Minor version = %d\n", MinorVersion));
|
DEBUG((EFI_D_INFO, "%a\n", SimicsStr));
|
DEBUG((EFI_D_INFO, "=============================================\n"));
|
}
|
}
|
|
VOID
|
DebugDumpCmos (
|
VOID
|
)
|
{
|
UINT8 Loop;
|
|
DEBUG ((EFI_D_INFO, "CMOS:\n"));
|
|
for (Loop = 0; Loop < 0x80; Loop++) {
|
if ((Loop % 0x10) == 0) {
|
DEBUG ((EFI_D_INFO, "%02x:", Loop));
|
}
|
DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
|
if ((Loop % 0x10) == 0xf) {
|
DEBUG ((EFI_D_INFO, "\n"));
|
}
|
}
|
}
|
|
|
/**
|
Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
|
Set the mMaxCpuCount variable.
|
**/
|
VOID
|
MaxCpuCountInitialization (
|
VOID
|
)
|
{
|
mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
|
return;
|
}
|
|
/**
|
Determine if S3 support is explicitly enabled.
|
|
@retval TRUE If S3 support is explicitly enabled. Other functions in this
|
library may be called (subject to their individual
|
restrictions).
|
|
FALSE Otherwise. This includes unavailability of the firmware
|
configuration interface. No other function in this library
|
must be called.
|
**/
|
BOOLEAN
|
EFIAPI
|
QemuFwCfgS3Enabled(
|
VOID
|
)
|
{
|
//TO DO IF NEEDED
|
return TRUE;
|
}
|
|
/**
|
Perform Platform PEI initialization.
|
|
@param FileHandle Handle of the file being invoked.
|
@param PeiServices Describes the list of possible PEI Services.
|
|
@return EFI_SUCCESS The PEIM initialized successfully.
|
|
**/
|
EFI_STATUS
|
EFIAPI
|
InitializePlatform (
|
IN EFI_PEI_FILE_HANDLE FileHandle,
|
IN CONST EFI_PEI_SERVICES **PeiServices
|
)
|
{
|
EFI_STATUS Status;
|
|
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
|
|
SimicsVersionCheck ();
|
DebugDumpCmos ();
|
|
if (QemuFwCfgS3Enabled ()) {
|
DEBUG ((EFI_D_INFO, "S3 support was detected on SIMICS\n"));
|
mS3Supported = TRUE;
|
Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
|
ASSERT_EFI_ERROR (Status);
|
}
|
AddressWidthInitialization ();
|
MaxCpuCountInitialization ();
|
|
mHostBridgeDevId = PciRead16(SIMICS_HOSTBRIDGE_DID);
|
|
if (FeaturePcdGet (PcdSmmSmramRequire)) {
|
X58TsegMbytesInitialization ();
|
}
|
|
PublishPeiMemory ();
|
|
InitializeRamRegions ();
|
|
if (mBootMode != BOOT_ON_S3_RESUME) {
|
if (!FeaturePcdGet (PcdSmmSmramRequire)) {
|
ReserveEmuVariableNvStore ();
|
}
|
MemMapInitialization ();
|
}
|
|
MiscInitialization ();
|
InstallFeatureControlCallback ();
|
|
return EFI_SUCCESS;
|
}
|
