/** @file
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Memory Detection for Virtual Machines.
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Copyright (c) 2006 - 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// The package level header files this module uses
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//
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#include <PiPei.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PeimEntryPoint.h>
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#include <Library/ResourcePublicationLib.h>
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#include <Library/MtrrLib.h>
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#include <Library/CmosAccessLib.h>
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#include <SimicsPlatforms.h>
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#include <Guid/SmramMemoryReserve.h>
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#include <CmosMap.h>
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#include "Platform.h"
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UINT8 mPhysMemAddressWidth;
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STATIC UINT32 mS3AcpiReservedMemoryBase;
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STATIC UINT32 mS3AcpiReservedMemorySize;
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STATIC UINT16 mX58TsegMbytes;
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VOID
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X58TsegMbytesInitialization(
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VOID
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)
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{
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if (mHostBridgeDevId != INTEL_ICH10_DEVICE_ID) {
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DEBUG ((
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DEBUG_ERROR,
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"%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
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"only DID=0x%04x (X58) is supported\n",
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__FUNCTION__,
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mHostBridgeDevId,
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INTEL_ICH10_DEVICE_ID
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));
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ASSERT (FALSE);
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CpuDeadLoop ();
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}
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//
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// Check if QEMU offers an extended TSEG.
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//
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// This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
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// register, and reading back the register.
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//
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// On a QEMU machine type that does not offer an extended TSEG, the initial
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// write overwrites whatever value a malicious guest OS may have placed in
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// the (unimplemented) register, before entering S3 or rebooting.
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// Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
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//
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// On a QEMU machine type that offers an extended TSEG, the initial write
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// triggers an update to the register. Subsequently, the value read back
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// (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
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// number of megabytes.
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//
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mX58TsegMbytes = FixedPcdGet8(PcdX58TsegMbytes);
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return;
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}
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/**
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Get the system memory size below 4GB
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@return The size of system memory below 4GB
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**/
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UINT32
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GetSystemMemorySizeBelow4gb (
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VOID
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)
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{
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UINT32 Size;
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//
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// CMOS 0x34/0x35 specifies the system memory above 16 MB.
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// * The size is specified in 64kb chunks
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// * Since this is memory above 16MB, the 16MB must be added
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// into the calculation to get the total memory size.
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//
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Size = (UINT32) ((CmosRead16 (CMOS_SYSTEM_MEM_ABOVE_16MB_LOW_BYTE) << 16)
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+ SIZE_16MB);
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return Size;
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}
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/**
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Get the system memory size above 4GB
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@return The size of system memory above 4GB
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**/
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STATIC
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UINT64
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GetSystemMemorySizeAbove4gb (
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)
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{
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UINT32 Size;
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//
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// CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
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// * The size is specified in 64kb chunks
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//
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Size = (CmosRead16 (CMOS_SYSTEM_MEM_ABOVE_4GB_MIDDLE_BYTE) << 8)
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+ CmosRead8 (CMOS_SYSTEM_MEM_ABOVE_4GB_LOW_BYTE);
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return LShiftU64 (Size, 16);
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}
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/**
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Return the highest address that DXE could possibly use, plus one.
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**/
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STATIC
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UINT64
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GetFirstNonAddress (
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VOID
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)
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{
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UINT64 FirstNonAddress;
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UINT64 Pci64Base, Pci64Size;
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FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();
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//
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// If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
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// resources to 32-bit anyway. See DegradeResource() in
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// "PciResourceSupport.c".
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//
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#ifdef MDE_CPU_IA32
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if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
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return FirstNonAddress;
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}
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#endif
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//
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// Otherwise, in order to calculate the highest address plus one, we must
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// consider the 64-bit PCI host aperture too. Fetch the default size.
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//
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Pci64Size = PcdGet64 (PcdPciMmio64Size);
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if (Pci64Size == 0) {
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if (mBootMode != BOOT_ON_S3_RESUME) {
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DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n",
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__FUNCTION__));
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PcdSet64S (PcdPciMmio64Size, 0);
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}
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//
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// There's nothing more to do; the amount of memory above 4GB fully
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// determines the highest address plus one. The memory hotplug area (see
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// below) plays no role for the firmware in this case.
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//
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return FirstNonAddress;
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}
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//
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// SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
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// that the host can map it with 1GB hugepages. Follow suit.
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//
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Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);
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Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);
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//
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// The 64-bit PCI host aperture should also be "naturally" aligned. The
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// alignment is determined by rounding the size of the aperture down to the
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// next smaller or equal power of two. That is, align the aperture by the
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// largest BAR size that can fit into it.
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//
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Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));
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if (mBootMode != BOOT_ON_S3_RESUME) {
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//
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// The core PciHostBridgeDxe driver will automatically add this range to
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// the GCD memory space map through our PciHostBridgeLib instance; here we
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// only need to set the PCDs.
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//
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PcdSet64S (PcdPciMmio64Base, Pci64Base);
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PcdSet64S (PcdPciMmio64Size, Pci64Size);
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DEBUG ((EFI_D_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
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__FUNCTION__, Pci64Base, Pci64Size));
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}
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//
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// The useful address space ends with the 64-bit PCI host aperture.
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//
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FirstNonAddress = Pci64Base + Pci64Size;
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return FirstNonAddress;
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}
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/**
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Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
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**/
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VOID
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AddressWidthInitialization (
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VOID
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)
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{
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UINT64 FirstNonAddress;
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//
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// As guest-physical memory size grows, the permanent PEI RAM requirements
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// are dominated by the identity-mapping page tables built by the DXE IPL.
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// The DXL IPL keys off of the physical address bits advertized in the CPU
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// HOB. To conserve memory, we calculate the minimum address width here.
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//
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FirstNonAddress = GetFirstNonAddress ();
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mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
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//
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// If FirstNonAddress is not an integral power of two, then we need an
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// additional bit.
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//
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if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {
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++mPhysMemAddressWidth;
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}
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//
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// The minimum address width is 36 (covers up to and excluding 64 GB, which
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// is the maximum for Ia32 + PAE). The theoretical architecture maximum for
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// X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
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// can simply assert that here, since 48 bits are good enough for 256 TB.
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//
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if (mPhysMemAddressWidth <= 36) {
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mPhysMemAddressWidth = 36;
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}
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ASSERT (mPhysMemAddressWidth <= 48);
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}
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/**
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Calculate the cap for the permanent PEI memory.
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**/
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STATIC
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UINT32
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GetPeiMemoryCap (
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VOID
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)
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{
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BOOLEAN Page1GSupport;
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UINT32 RegEax;
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UINT32 RegEdx;
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UINT32 Pml4Entries;
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UINT32 PdpEntries;
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UINTN TotalPages;
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//
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// If DXE is 32-bit, then just return the traditional 64 MB cap.
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//
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#ifdef MDE_CPU_IA32
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if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
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return SIZE_64MB;
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}
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#endif
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//
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// Dependent on physical address width, PEI memory allocations can be
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// dominated by the page tables built for 64-bit DXE. So we key the cap off
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// of those. The code below is based on CreateIdentityMappingPageTables() in
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// "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
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//
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Page1GSupport = FALSE;
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if (PcdGetBool (PcdUse1GPageTable)) {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT26) != 0) {
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Page1GSupport = TRUE;
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}
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}
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}
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if (mPhysMemAddressWidth <= 39) {
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Pml4Entries = 1;
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PdpEntries = 1 << (mPhysMemAddressWidth - 30);
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ASSERT (PdpEntries <= 0x200);
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} else {
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Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
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ASSERT (Pml4Entries <= 0x200);
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PdpEntries = 512;
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}
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TotalPages = Page1GSupport ? Pml4Entries + 1 :
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(PdpEntries + 1) * Pml4Entries + 1;
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ASSERT (TotalPages <= 0x40201);
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//
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// Add 64 MB for miscellaneous allocations. Note that for
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// mPhysMemAddressWidth values close to 36, the cap will actually be
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// dominated by this increment.
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//
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return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);
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}
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/**
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Publish PEI core memory
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@return EFI_SUCCESS The PEIM initialized successfully.
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**/
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EFI_STATUS
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PublishPeiMemory (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS MemoryBase;
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UINT64 MemorySize;
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UINT32 LowerMemorySize;
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UINT32 PeiMemoryCap;
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LowerMemorySize = GetSystemMemorySizeBelow4gb ();
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if (FeaturePcdGet (PcdSmmSmramRequire)) {
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//
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// TSEG is chipped from the end of low RAM
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//
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LowerMemorySize -= mX58TsegMbytes * SIZE_1MB;
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}
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//
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// If S3 is supported, then the S3 permanent PEI memory is placed next,
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// downwards. Its size is primarily dictated by CpuMpPei. The formula below
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// is an approximation.
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//
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if (mS3Supported) {
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mS3AcpiReservedMemorySize = SIZE_512KB +
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mMaxCpuCount *
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PcdGet32 (PcdCpuApStackSize);
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mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;
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LowerMemorySize = mS3AcpiReservedMemoryBase;
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}
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if (mBootMode == BOOT_ON_S3_RESUME) {
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MemoryBase = mS3AcpiReservedMemoryBase;
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MemorySize = mS3AcpiReservedMemorySize;
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} else {
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PeiMemoryCap = GetPeiMemoryCap ();
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DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
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__FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));
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//
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// Determine the range of memory to use during PEI
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//
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// Technically we could lay the permanent PEI RAM over SEC's temporary
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// decompression and scratch buffer even if "secure S3" is needed, since
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// their lifetimes don't overlap. However, PeiFvInitialization() will cover
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// RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory
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// allocation HOB, and other allocations served from the permanent PEI RAM
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// shouldn't overlap with that HOB.
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//
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MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?
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PcdGet32 (PcdSimicsDecompressionScratchEnd) :
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PcdGet32 (PcdSimicsDxeMemFvBase) + PcdGet32 (PcdSimicsDxeMemFvSize);
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MemorySize = LowerMemorySize - MemoryBase;
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}
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DEBUG((EFI_D_INFO, "MemoryBase=0x%lx MemorySize=0x%lx\n", MemoryBase, MemorySize));
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//
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// Publish this memory to the PEI Core
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//
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Status = PublishSystemMemory(MemoryBase, MemorySize);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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/**
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Peform Memory Detection for QEMU / KVM
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**/
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STATIC
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VOID
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QemuInitializeRam (
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VOID
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)
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{
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UINT64 LowerMemorySize;
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UINT64 UpperMemorySize;
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UINTN BufferSize;
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UINT8 SmramIndex;
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UINT8 SmramRanges;
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EFI_PEI_HOB_POINTERS Hob;
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EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
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UINT8 Index;
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DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));
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//
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// Determine total memory size available
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//
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LowerMemorySize = GetSystemMemorySizeBelow4gb ();
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UpperMemorySize = GetSystemMemorySizeAbove4gb ();
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if (mBootMode == BOOT_ON_S3_RESUME) {
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//
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// Create the following memory HOB as an exception on the S3 boot path.
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//
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// Normally we'd create memory HOBs only on the normal boot path. However,
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// CpuMpPei specifically needs such a low-memory HOB on the S3 path as
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// well, for "borrowing" a subset of it temporarily, for the AP startup
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// vector.
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//
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// CpuMpPei saves the original contents of the borrowed area in permanent
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// PEI RAM, in a backup buffer allocated with the normal PEI services.
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// CpuMpPei restores the original contents ("returns" the borrowed area) at
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// End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
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// transferring control to the OS's wakeup vector in the FACS.
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//
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// We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
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// restore the original contents. Furthermore, we expect all such PEIMs
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// (CpuMpPei included) to claim the borrowed areas by producing memory
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// allocation HOBs, and to honor preexistent memory allocation HOBs when
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// looking for an area to borrow.
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//
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AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
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} else {
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//
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// Create memory HOBs
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//
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AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
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if (FeaturePcdGet (PcdSmmSmramRequire)) {
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UINT32 TsegSize;
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TsegSize = mX58TsegMbytes * SIZE_1MB;
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AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);
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AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,
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TRUE);
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BufferSize = sizeof(EFI_SMRAM_HOB_DESCRIPTOR_BLOCK);
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SmramRanges = 1;
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Hob.Raw = BuildGuidHob(
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&gEfiSmmSmramMemoryGuid,
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BufferSize
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);
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ASSERT(Hob.Raw);
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SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)(Hob.Raw);
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SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges;
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SmramIndex = 0;
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for (Index = 0; Index < SmramRanges; Index++) {
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//
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// This is an SMRAM range, create an SMRAM descriptor
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//
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SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = LowerMemorySize - TsegSize;
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SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = LowerMemorySize - TsegSize;
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SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = TsegSize;
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SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE;
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SmramIndex++;
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}
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} else {
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AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
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}
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//
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// If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
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// entries. Otherwise, create a single memory HOB with the flat >=4GB
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// memory size read from the CMOS.
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//
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if (UpperMemorySize != 0) {
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AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
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}
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}
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}
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/**
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Publish system RAM and reserve memory regions
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**/
|
VOID
|
InitializeRamRegions (
|
VOID
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)
|
{
|
QemuInitializeRam ();
|
|
if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {
|
//
|
// This is the memory range that will be used for PEI on S3 resume
|
//
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BuildMemoryAllocationHob (
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mS3AcpiReservedMemoryBase,
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mS3AcpiReservedMemorySize,
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EfiACPIMemoryNVS
|
);
|
|
//
|
// Cover the initial RAM area used as stack and temporary PEI heap.
|
//
|
// This is reserved as ACPI NVS so it can be used on S3 resume.
|
//
|
BuildMemoryAllocationHob (
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PcdGet32 (PcdSimicsSecPeiTempRamBase),
|
PcdGet32 (PcdSimicsSecPeiTempRamSize),
|
EfiACPIMemoryNVS
|
);
|
|
//
|
// SEC stores its table of GUIDed section handlers here.
|
//
|
BuildMemoryAllocationHob (
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PcdGet64 (PcdGuidedExtractHandlerTableAddress),
|
PcdGet32 (PcdGuidedExtractHandlerTableSize),
|
EfiACPIMemoryNVS
|
);
|
|
}
|
|
if (mBootMode != BOOT_ON_S3_RESUME) {
|
if (!FeaturePcdGet (PcdSmmSmramRequire)) {
|
//
|
// Reserve the lock box storage area
|
//
|
// Since this memory range will be used on S3 resume, it must be
|
// reserved as ACPI NVS.
|
//
|
// If S3 is unsupported, then various drivers might still write to the
|
// LockBox area. We ought to prevent DXE from serving allocation requests
|
// such that they would overlap the LockBox storage.
|
//
|
ZeroMem (
|
(VOID*)(UINTN) PcdGet32 (PcdSimicsLockBoxStorageBase),
|
(UINTN) PcdGet32 (PcdSimicsLockBoxStorageSize)
|
);
|
BuildMemoryAllocationHob (
|
(EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdSimicsLockBoxStorageBase),
|
(UINT64)(UINTN) PcdGet32 (PcdSimicsLockBoxStorageSize),
|
mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
|
);
|
}
|
|
if (FeaturePcdGet (PcdSmmSmramRequire)) {
|
UINT32 TsegSize;
|
|
//
|
// Make sure the TSEG area that we reported as a reserved memory resource
|
// cannot be used for reserved memory allocations.
|
//
|
TsegSize = mX58TsegMbytes * SIZE_1MB;
|
BuildMemoryAllocationHob (
|
GetSystemMemorySizeBelow4gb() - TsegSize,
|
TsegSize,
|
EfiReservedMemoryType
|
);
|
}
|
}
|
}
|
