/** @file
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CPU power management control methods
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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DefinitionBlock (
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"CPUPM.aml",
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"SSDT",
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0x01,
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"SsgPmm",
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"CpuPm",
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0x0010
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)
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{
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External(\_PR.CPU0, DeviceObj)
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External(CFGD, FieldUnitObj)
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Scope(\)
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{
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// Config DWord, modified during POST
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// Bit definitions are the same as PPMFlags:
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// CFGD[0] = PPM_GV3 = GV3
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// CFGD[1] = PPM_TURBO = Turbo Mode
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// CFGD[2] = PPM_SUPER_LFM = N/2 Ratio
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// CFGD[4] = PPM_C1 = C1 Capable, Enabled
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// CFGD[5] = PPM_C2 = C2 Capable, Enabled
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// CFGD[6] = PPM_C3 = C3 Capable, Enabled
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// CFGD[7] = PPM_C4 = C4 Capable, Enabled
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// CFGD[8] = PPM_C5 = C5/Deep C4 Capable, Enabled
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// CFGD[9] = PPM_C6 = C6 Capable, Enabled
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// CFGD[10] = PPM_C1E = C1E Enabled
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// CFGD[11] = PPM_C2E = C2E Enabled
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// CFGD[12] = PPM_C3E = C3E Enabled
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// CFGD[13] = PPM_C4E = C4E Enabled
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// CFGD[14] = PPM_HARD_C4E = Hard C4E Capable, Enabled
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// CFGD[16] = PPM_TM1 = Thermal Monitor 1
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// CFGD[17] = PPM_TM2 = Thermal Monitor 2
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// CFGD[19] = PPM_PHOT = Bi-directional ProcHot
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// CFGD[21] = PPM_MWAIT_EXT = MWAIT extensions supported
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// CFGD[24] = PPM_CMP = CMP supported, Enabled
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// CFGD[28] = PPM_TSTATE = CPU T states supported
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//
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// Name(CFGD, 0x80000000)
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// External Defined in GNVS
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Name(PDC0,0x80000000) // CPU0 _PDC Flags.
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// We load it in AcpiPlatform
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//Name(SSDT,Package()
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//{
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// "CPU0IST ", 0x80000000, 0x80000000,
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// "CPU1IST ", 0x80000000, 0x80000000,
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// "CPU0CST ", 0x80000000, 0x80000000,
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// "CPU1CST ", 0x80000000, 0x80000000,
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//})
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}
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Scope(\_PR.CPU0)
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{
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Method(_PDC, 1)
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{
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//
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// Store result of PDC.
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//
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CreateDWordField(Arg0,8,CAP0) // Point to 3rd DWORD.
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Store(CAP0,PDC0) // Store It in PDC0.
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}
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}
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}
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