/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _EFI_SYSTEM_BOARD_PPI_H_
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#define _EFI_SYSTEM_BOARD_PPI_H_
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#include <Platform.h>
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#include <Library/MmPciBaseLib.h>
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#include <Pi/PiHob.h>
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// GUID
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#include <Guid/SetupVariable.h>
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#include <Guid/SocketIioVariable.h>
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// PPI
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#include <Ppi/PchPolicy.h>
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#include <Ppi/SystemBoard.h>
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#include <Ppi/ReadOnlyVariable2.h>
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#include <Ppi/Smbus2.h>
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// Library
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PciLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/HobLib.h>
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#include <Library/PciExpressLib.h>
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#include <Library/GpioLib.h>
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#include <Library/PeiServicesTablePointerLib.h>
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#include <Library/PchInfoLib.h>
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#include <Platform.h>
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#include <GpioPinsSklH.h>
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#include <Library/GpioLib.h>
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#include <IioBifurcationSlotTable.h>
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// CMOS access Port address
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#define LAST_CMOS_BYTE 0x7F
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#define NMI_OFF 0x80
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#define B_PCH_RTC_REGB_SRBRST 0x02 // Value to be reset to during POST
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#define R_PCH_RTC_REGD 0x0D // CMOS Register D Status
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#define R_PCH_RTC_REGE 0x0E // CMOS Register E Status
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#define B_PCH_RTC_REGE_INVTIM 0x04 // CMOS invalid time found
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#define TIMER1_CONTROL_PORT 0x43
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#define TIMER1_COUNT_PORT 0x41
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#define LOAD_COUNTER1_LSB 0x54
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#define COUNTER1_COUNT 0x12
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//
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// Reset Generator I/O Port
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//
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#define RESET_GENERATOR_PORT 0xCF9
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//-----------------------------------------------------------------------;
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// PCH: Chipset Configuration Register Equates
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//-----------------------------------------------------------------------;
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#define ICH_RCRB_IRQ0 0
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#define ICH_RCRB_IRQA 1
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#define ICH_RCRB_IRQB 2
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#define ICH_RCRB_IRQC 3
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#define ICH_RCRB_IRQD 4
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#define ICH_RCRB_PIRQA 0
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#define ICH_RCRB_PIRQB 1
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#define ICH_RCRB_PIRQC 2
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#define ICH_RCRB_PIRQD 3
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#define ICH_RCRB_PIRQE 4
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#define ICH_RCRB_PIRQF 5
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#define ICH_RCRB_PIRQG 6
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#define ICH_RCRB_PIRQH 7
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//
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// From WBG Soft Straps WIP.xlsx
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//
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#define WBG_DOWNSKU_STRAP_DSKU 0x80046000
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#define WBG_DOWNSKU_STRAP_BSKU 0x8004E003
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#define WBG_DOWNSKU_STRAP_TSKU 0x00044000
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#define PCHSTRAP_9 9
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#define PCHSTRAP_10 10
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#define PCHSTRAP_16 16
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#define PCHSTRAP_17 17
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#define RESET_PORT 0x0CF9
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#define CLEAR_RESET_BITS 0x0F1
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#define COLD_RESET 0x02 // Set bit 1 for cold reset
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#define RST_CPU 0x04 // Setting this bit triggers a reset of the CPU
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#define FULL_RESET 0x08 // Set bit 4 with bit 1 for full reset
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//
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// PPI functions
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//
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VOID
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SetBifurcations(
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN IIO_BIFURCATION_ENTRY *BifurcationTable,
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IN UINT8 BifurcationEntries
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);
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VOID
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EnableHotPlug (
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN UINT8 Port,
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IN UINT8 VppPort,
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IN UINT8 VppAddress,
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IN UINT8 PortOwnership
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);
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VOID
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ConfigSlots (
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN IIO_SLOT_CONFIG_ENTRY *Slot,
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IN UINT8 SlotEntries
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);
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VOID
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OverrideConfigSlots (
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN IIO_SLOT_CONFIG_ENTRY *Slot,
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IN UINT8 SlotEntries
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);
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VOID
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CalculatePEXPHideFromIouBif (
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IN UINT8 Iou,
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IN UINT8 IioIndex,
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IN OUT IIO_GLOBALS *IioGlobalData
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);
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VOID
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DumpIioConfiguration(
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IN UINT8 iio,
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IN IIO_GLOBALS *IioGlobalData
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);
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VOID
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OverrideDefaultBifSlots(
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IN IIO_GLOBALS *IioGlobalData
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);
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UINT8
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GetUplinkPortInformationCommon (
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IN UINT8 IioIndex
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);
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VOID
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SystemIioPortBifurcationInitCommon (
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IIO_GLOBALS *IioGlobalData,
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IIO_BIFURCATION_ENTRY **BifurcationTable,
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UINT8 *BifurcationEntries,
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IIO_SLOT_CONFIG_ENTRY **SlotTable,
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UINT8 *SlotEntries
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);
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VOID
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SystemHideIioPortsCommon(
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IIO_GLOBALS *IioGlobalData,
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UINT8 IioIndex
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);
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UINT8
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GetUplinkPortInformation (
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IN UINT8 IioIndex
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);
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VOID
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SystemIioPortBifurcationInit (
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IN IIO_GLOBALS *IioGlobalData
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);
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#endif
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