/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "SystemBoardPei.h"
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <IioBifurcationSlotTable.h>
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extern IIO_BIFURCATION_ENTRY mIioBifurcationTable[];
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extern UINT8 mIioBifurcationTableEntries;
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extern IIO_SLOT_CONFIG_ENTRY mIioSlotTable[];
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extern UINT8 mIioSlotTableEntries;
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//
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// System board PPI structure
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//
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static SYSTEM_BOARD_PPI mSystemBoardPpi = {
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SystemIioPortBifurcationInit, // Set IIO Bifurcation ports configuration
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GetUplinkPortInformation,
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};
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static EFI_PEI_PPI_DESCRIPTOR mSystemBoardPpiDesc = {
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EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gEfiPeiSystemBoardPpiGuid,
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&mSystemBoardPpi
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};
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/**
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GetUplinkPortInformation - Get uplink port information
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@param IioIndex - socket ID.
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@retval PortIndex for uplink port
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**/
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UINT8
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EFIAPI
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GetUplinkPortInformation (
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IN UINT8 IioIndex
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)
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{
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UINT8 UplinkPortIndex;
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UplinkPortIndex = GetUplinkPortInformationCommon(IioIndex);
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return UplinkPortIndex;
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}
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/**
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SystemIioPortBifurcationInit - Program the UDS data structure with OEM IIO init values
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for SLOTs and Bifurcation.
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@param mSB - pointer to this protocol
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@param IioUds - Pointer to the IIO UDS datastructure.
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@retval EFI_SUCCESS
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**/
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VOID
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InternalSystemIioPortBifurcationInitCommon (
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN OUT IIO_BIFURCATION_ENTRY **BifurcationTable,
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IN OUT UINT8 *BifurcationEntries,
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IN OUT IIO_SLOT_CONFIG_ENTRY **SlotTable,
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IN OUT UINT8 *SlotEntries
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)
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{
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UINT8 PortIndex;//, iio;
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/// This function outline:
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//// 1 Based on platform apply the default bifurcation and slot configuration.
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//// 2 Apply dynamic overrides based on GPIO and other configurations.
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//// 3 Hide unused ports due bifurcation.
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for (PortIndex = 0; PortIndex < MAX_SOCKET*NUMBER_PORTS_PER_SOCKET; PortIndex++) {
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IioGlobalData->SetupData.PEXPHIDE[PortIndex] = 0;
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IioGlobalData->SetupData.HidePEXPMenu[PortIndex] = 0;
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}
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*BifurcationEntries = 0;
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*SlotEntries = 0;
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// Purley Intel boards are not Multi-PCH
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IioGlobalData->IioVar.IioVData.MultiPch = 0;
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*BifurcationTable = (IIO_BIFURCATION_ENTRY *)(UINTN)PcdGet64 (PcdIioBifurcationTable);
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*BifurcationEntries = PcdGet8 (PcdIioBifurcationTableEntries);
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*SlotTable = (IIO_SLOT_CONFIG_ENTRY *)(UINTN)PcdGet64 (PcdIioSlotTable);
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*SlotEntries = PcdGet8 (PcdIioSlotTableEntries);
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}
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/**
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SystemIioPortBifurcationInit - Program the IIO_GLOBALS data structure with OEM IIO init values
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for SLOTs and Bifurcation.
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@param mSB - pointer to this protocol
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@param IioUds - Pointer to the IIO UDS datastructure.
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@retval EFI_SUCCESS
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**/
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VOID
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SystemIioPortBifurcationInit (
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IN IIO_GLOBALS *IioGlobalData
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)
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{
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UINT8 IioIndex;
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IIO_BIFURCATION_ENTRY *BifurcationTable = NULL;
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UINT8 BifurcationEntries;
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IIO_SLOT_CONFIG_ENTRY *SlotTable = NULL;
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UINT8 SlotEntries;
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// This function outline:
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// 1. Based on platform apply the default bifurcation and slot configuration.
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// 2. Apply dynamic overrides based on GPIO and other configurations.
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// 3. Hide unused ports due bifurcation.
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SystemIioPortBifurcationInitCommon(IioGlobalData, &BifurcationTable, &BifurcationEntries, &SlotTable, &SlotEntries);
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/// Set the default bifurcations for this platform.
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SetBifurcations(IioGlobalData, BifurcationTable, BifurcationEntries);
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ConfigSlots(IioGlobalData, SlotTable, SlotEntries);
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OverrideConfigSlots(IioGlobalData, SlotTable, SlotEntries);
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// All overrides have been applied now.
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// Hide root ports whose lanes are assigned preceding ports.
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for (IioIndex = Iio_Socket0; IioIndex < MaxIIO; IioIndex++) {
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if (IioGlobalData->IioVar.IioVData.SocketPresent[IioIndex]) {
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SystemHideIioPortsCommon(IioGlobalData, IioIndex);
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}
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}
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}
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/**
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This function dump raw data.
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@param Data raw data
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@param Size raw data size
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**/
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VOID
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InternalDumpData (
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IN UINT8 *Data,
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IN UINTN Size
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)
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{
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UINTN Index;
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for (Index = 0; Index < Size; Index++) {
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DEBUG ((EFI_D_INFO, "%02x", (UINTN)Data[Index]));
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}
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}
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/**
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This function dump raw data with colume format.
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@param Data raw data
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@param Size raw data size
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**/
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VOID
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InternalDumpHex (
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IN UINT8 *Data,
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IN UINTN Size
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)
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{
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UINTN Index;
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UINTN Count;
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UINTN Left;
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#define COLUME_SIZE (16 * 2)
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Count = Size / COLUME_SIZE;
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Left = Size % COLUME_SIZE;
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for (Index = 0; Index < Count; Index++) {
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DEBUG ((EFI_D_INFO, "%04x: ", Index * COLUME_SIZE));
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InternalDumpData (Data + Index * COLUME_SIZE, COLUME_SIZE);
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DEBUG ((EFI_D_INFO, "\n"));
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}
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if (Left != 0) {
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DEBUG ((EFI_D_INFO, "%04x: ", Index * COLUME_SIZE));
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InternalDumpData (Data + Index * COLUME_SIZE, Left);
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DEBUG ((EFI_D_INFO, "\n"));
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}
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}
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VOID
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DumpConfig (
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VOID
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)
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{
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DEBUG ((DEBUG_INFO, "PcdSetupData - 0x%x\n", PcdGetSize (PcdSetupData)));
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InternalDumpHex (PcdGetPtr (PcdSetupData), PcdGetSize (PcdSetupData));
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DEBUG ((DEBUG_INFO, "PcdPchRcConfigurationData - 0x%x\n", PcdGetSize (PcdPchRcConfigurationData)));
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InternalDumpHex (PcdGetPtr (PcdPchRcConfigurationData), PcdGetSize (PcdPchRcConfigurationData));
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DEBUG ((DEBUG_INFO, "PcdSocketIioConfigData - 0x%x\n", PcdGetSize (PcdSocketIioConfigData)));
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InternalDumpHex (PcdGetPtr (PcdSocketIioConfigData), PcdGetSize (PcdSocketIioConfigData));
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DEBUG ((DEBUG_INFO, "PcdSocketCommonRcConfigData - 0x%x\n", PcdGetSize (PcdSocketCommonRcConfigData)));
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InternalDumpHex (PcdGetPtr (PcdSocketCommonRcConfigData), PcdGetSize (PcdSocketCommonRcConfigData));
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DEBUG ((DEBUG_INFO, "PcdSocketMpLinkConfigData - 0x%x\n", PcdGetSize (PcdSocketMpLinkConfigData)));
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InternalDumpHex (PcdGetPtr (PcdSocketMpLinkConfigData), PcdGetSize (PcdSocketMpLinkConfigData));
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DEBUG ((DEBUG_INFO, "PcdSocketMemoryConfigData - 0x%x\n", PcdGetSize (PcdSocketMemoryConfigData)));
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InternalDumpHex (PcdGetPtr (PcdSocketMemoryConfigData), PcdGetSize (PcdSocketMemoryConfigData));
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DEBUG ((DEBUG_INFO, "PcdSocketPowerManagementConfigData - 0x%x\n", PcdGetSize (PcdSocketPowerManagementConfigData)));
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InternalDumpHex (PcdGetPtr (PcdSocketPowerManagementConfigData), PcdGetSize (PcdSocketPowerManagementConfigData));
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DEBUG ((DEBUG_INFO, "PcdSocketProcessorCoreConfigData - 0x%x\n", PcdGetSize (PcdSocketProcessorCoreConfigData)));
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InternalDumpHex (PcdGetPtr (PcdSocketProcessorCoreConfigData), PcdGetSize (PcdSocketProcessorCoreConfigData));
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}
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//
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// PEI entry point - SystemBoardPpi entry point
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//
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/**
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PEI system board PPI intialization main entry point. This will setup up a PPI that will handle providing system board level
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configuration for the platform.
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@param FileHandle Pointer to the PEIM FFS file header.
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@param PeiServices General purpose services available to every PEIM.
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@retval EFI_SUCCESS Operation completed successfully.
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@retval Otherwise System board initialization failed.
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**/
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EFI_STATUS
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EFIAPI
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SystemBoardPeiEntry (
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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EFI_STATUS Status;
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DEBUG ((EFI_D_ERROR, "--> SystemBoard PEI BoardDetection\n"));
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//DumpConfig ();
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//
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// Initialize system board information PPI
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//
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Status = PeiServicesInstallPpi(&mSystemBoardPpiDesc);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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