/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Platform.h>
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#include <Register/PchRegsUsb.h>
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#include <PchLimits.h>
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#include <PchPolicyCommon.h>
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#include <IioBifurcationSlotTable.h>
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VOID
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SetBifurcations(
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN IIO_BIFURCATION_ENTRY *BifurcationTable,
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IN UINT8 BifurcationEntries
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)
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{
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UINT8 Socket;
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UINT8 Iou;
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UINT8 Index;
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for (Index = 0; Index < BifurcationEntries ; Index++) {
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Socket = BifurcationTable[Index].Socket;
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Iou = BifurcationTable[Index].IouNumber;
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switch (Iou) {
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case Iio_Iou0:
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if (IioGlobalData->SetupData.ConfigIOU0[Socket]==IIO_BIFURCATE_AUTO) {
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IioGlobalData->SetupData.ConfigIOU0[Socket] = BifurcationTable[Index].Bifurcation;
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}
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break;
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case Iio_Iou1:
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if (IioGlobalData->SetupData.ConfigIOU1[Socket] == IIO_BIFURCATE_AUTO) {
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IioGlobalData->SetupData.ConfigIOU1[Socket] = BifurcationTable[Index].Bifurcation;
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}
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break;
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case Iio_Iou2:
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if (IioGlobalData->SetupData.ConfigIOU2[Socket]==IIO_BIFURCATE_AUTO) {
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IioGlobalData->SetupData.ConfigIOU2[Socket] = BifurcationTable[Index].Bifurcation;
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}
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break;
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case Iio_Mcp0:
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if (IioGlobalData->SetupData.ConfigMCP0[Socket] == IIO_BIFURCATE_AUTO) {
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IioGlobalData->SetupData.ConfigMCP0[Socket] = BifurcationTable[Index].Bifurcation;
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}
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break;
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case Iio_Mcp1:
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if (IioGlobalData->SetupData.ConfigMCP1[Socket] == IIO_BIFURCATE_AUTO) {
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IioGlobalData->SetupData.ConfigMCP1[Socket] = BifurcationTable[Index].Bifurcation;
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}
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break;
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default:
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DEBUG((EFI_D_ERROR, "Invalid bifurcation table: Bad Iou (%d)", Iou));
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ASSERT(Iou);
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break;
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}
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}
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}
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VOID
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EnableHotPlug (
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN UINT8 Port,
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IN UINT8 VppPort,
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IN UINT8 VppAddress,
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IN UINT8 PortOwnership
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)
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{
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IioGlobalData->SetupData.SLOTHPCAP[Port]= ENABLE;
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IioGlobalData->SetupData.SLOTAIP[Port] = ENABLE; // Attention Indicator Present
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IioGlobalData->SetupData.SLOTPIP[Port] = ENABLE; // Power Indicator Present
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IioGlobalData->SetupData.SLOTMRLSP[Port]= ENABLE; // MRL Sensor Present
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IioGlobalData->SetupData.SLOTABP[Port] = ENABLE; // Attention Button Present
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IioGlobalData->SetupData.SLOTPCP[Port] = ENABLE; // Power Controlled Present
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if (PortOwnership == PCIEAIC_OCL_OWNERSHIP){
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IioGlobalData->SetupData.SLOTAIP[Port] = DISABLE; // Attention Indicator Present
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IioGlobalData->SetupData.SLOTPIP[Port] = DISABLE; // Power Indicator Present
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}
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if (PortOwnership == VMD_OWNERSHIP){
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IioGlobalData->SetupData.SLOTABP[Port] = DISABLE;
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IioGlobalData->SetupData.SLOTPCP[Port] = DISABLE;
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IioGlobalData->SetupData.SLOTMRLSP[Port]= DISABLE;
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}
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//
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// Set SLTCAP settings based on VMD/PCIe SSD Ownership
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//
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if ((PortOwnership == PCIEAIC_OCL_OWNERSHIP) ||
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(PortOwnership == VMD_OWNERSHIP)){
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IioGlobalData->SetupData.SLOTHPSUP[Port]= ENABLE; // HotPlug Surprise
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}
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if (VppPort!= VPP_PORT_MAX) {
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IioGlobalData->SetupData.VppEnable[Port]= ENABLE;
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IioGlobalData->SetupData.VppPort[Port]= VppPort;
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IioGlobalData->SetupData.VppAddress[Port] = VppAddress;
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} else {
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DEBUG((EFI_D_ERROR, "PCIE HOT Plug. Missing VPP values on slot table\n"));
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}
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}
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VOID
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ConfigSlots (
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN IIO_SLOT_CONFIG_ENTRY *Slot,
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IN UINT8 SlotEntries
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)
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{
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UINT8 Index;
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UINT8 Port;
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for (Index =0; Index < SlotEntries; Index ++) {
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Port=Slot[Index].PortIndex;
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if (Slot[Index].Hidden != NOT_HIDE) {
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IioGlobalData->SetupData.HidePEXPMenu[Port] = HIDE;
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IioGlobalData->SetupData.PEXPHIDE[Port]= HIDE;
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}
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/// Check if slot is assigned.
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if (Slot[Index].SlotNumber!= NO_SLT_IMP){
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IioGlobalData->SetupData.SLOTIMP[Port]= SLT_IMP;
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IioGlobalData->SetupData.SLOTPSP[Port]=Slot[Index].SlotNumber;
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IioGlobalData->SetupData.SLOTEIP[Port]=Slot[Index].InterLockPresent;
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if (Slot[Index].SlotPowerLimitScale!= PWR_SCL_MAX) {
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IioGlobalData->SetupData.SLOTSPLS[Port] = Slot[Index].SlotPowerLimitScale;
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IioGlobalData->SetupData.SLOTSPLV[Port] = Slot[Index].SlotPowerLimitValue;
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}
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if (Slot[Index].HotPlugCapable != DISABLE) {
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EnableHotPlug(IioGlobalData, Port, Slot[Index].VppPort, Slot[Index].VppAddress, REGULAR_PCIE_OWNERSHIP);
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}
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}
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}
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}
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/**
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Verify if and Slot should be implemented based on IOUX bifurcation settings.
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@param IioGlobalData Pointer to Iio Globals.
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@param Port - Port Index
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@retval TRUE/FALSE to determine if an slot shoudl be implemented or not
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based on the IOUX bifurcation settings in case user want to do an
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override and VMD is enabled.
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**/
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BOOLEAN
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SlotImplemented(
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN UINT8 Port
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){
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UINT8 IioIndex;
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UINT8 PortIndex;
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UINT8 Stack;
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BOOLEAN SlotImp = FALSE;
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IioIndex = Port/NUMBER_PORTS_PER_SOCKET;
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PortIndex = (Port - (NUMBER_PORTS_PER_SOCKET * IioIndex));
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// Stack = (((PortIndex + 3)/4) - 1) + (IioIndex*VMD_STACK_PER_SOCKET);
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Stack = IioGlobalData->IioVar.IioVData.StackPerPort[IioIndex][PortIndex];
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DEBUG((DEBUG_INFO, "SlotImplemented:IioIndex = %x, Stack = %x, Port = %x, PortIndex =%x\n", IioIndex, Stack, Port, PortIndex));
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switch(Stack){
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case IIO_PSTACK0:
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if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_x4x4x4x4){
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SlotImp = TRUE;
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} else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_x4x4xxx8){
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if ((PortIndex == PORT_1D_INDEX) || (PortIndex == PORT_1C_INDEX) || (PortIndex == PORT_1A_INDEX)){
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SlotImp = TRUE;
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}
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} else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_xxx8x4x4){
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if ((PortIndex == PORT_1C_INDEX) || (PortIndex == PORT_1B_INDEX) || (PortIndex == PORT_1A_INDEX)){
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SlotImp = TRUE;
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}
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} else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_xxx8xxx8){
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if ((PortIndex == PORT_1C_INDEX) || (PortIndex == PORT_1A_INDEX)){
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SlotImp = TRUE;
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}
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} else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_xxxxxx16){
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if (PortIndex == PORT_1A_INDEX){
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SlotImp = TRUE;
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}
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}
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break;
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case IIO_PSTACK1:
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if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_x4x4x4x4){
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SlotImp = TRUE;
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} else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_x4x4xxx8){
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if ((PortIndex == PORT_2D_INDEX) || (PortIndex == PORT_2C_INDEX) || (PortIndex == PORT_2A_INDEX)){
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SlotImp = TRUE;
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}
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} else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_xxx8x4x4){
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if ((PortIndex == PORT_2C_INDEX) || (PortIndex == PORT_2B_INDEX) || (PortIndex == PORT_2A_INDEX)){
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SlotImp = TRUE;
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}
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} else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_xxx8xxx8){
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if ((PortIndex == PORT_2C_INDEX) || (PortIndex == PORT_2A_INDEX)){
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SlotImp = TRUE;
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}
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} else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_xxxxxx16){
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if (PortIndex == PORT_2A_INDEX){
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SlotImp = TRUE;
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}
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}
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break;
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case IIO_PSTACK2:
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if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_x4x4x4x4){
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SlotImp = TRUE;
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} else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_x4x4xxx8){
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if ((PortIndex == PORT_3D_INDEX) || (PortIndex == PORT_3C_INDEX) || (PortIndex == PORT_3A_INDEX)){
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SlotImp = TRUE;
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}
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} else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_xxx8x4x4){
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if ((PortIndex == PORT_3C_INDEX) || (PortIndex == PORT_3B_INDEX) || (PortIndex == PORT_3A_INDEX)){
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SlotImp = TRUE;
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}
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} else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_xxx8xxx8){
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if ((PortIndex == PORT_3C_INDEX) || (PortIndex == PORT_3A_INDEX)){
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SlotImp = TRUE;
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}
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} else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_xxxxxx16){
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if (PortIndex == PORT_3A_INDEX){
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SlotImp = TRUE;
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}
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}
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break;
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}
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DEBUG((DEBUG_INFO, "SlotImplemented: = %x\n", SlotImp));
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return SlotImp;
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}
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/**
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Verify if VMD is enabled and override Slot conofgiration
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based on the VMD settings
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@param IioGlobalData Pointer to Iio Globals.
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@param Slot - Slot configuarion settings
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@param SlotEntries - Number of slot entries
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@retval None
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**/
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VOID
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OverrideConfigSlots (
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IN OUT IIO_GLOBALS *IioGlobalData,
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IN IIO_SLOT_CONFIG_ENTRY *Slot,
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IN UINT8 SlotEntries
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)
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{
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UINT8 Index;
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UINT8 Port;
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UINT8 IioIndex;
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UINT8 VmdPort;
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UINT8 Stack;
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for (Index =0; Index < SlotEntries; Index ++) {
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Port = Slot[Index].PortIndex;
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//
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// Check if Slot is capable of PcieSSD Solution and override the SLOT Config values
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//
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if (Slot[Index].PcieSSDCapable){
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IioIndex = Port/NUMBER_PORTS_PER_SOCKET;
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Stack = ((((Port - (NUMBER_PORTS_PER_SOCKET * IioIndex))+ 3)/4) - 1) + (IioIndex*VMD_STACK_PER_SOCKET);
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DEBUG((DEBUG_INFO, "Stack = %x, Port = %x\n", Stack, Port));
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//
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// check if VMD will own Pcie Root Port
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//
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if(IioGlobalData->SetupData.VMDEnabled[Stack]){
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VmdPort = ((IioIndex * VMD_PORTS_PER_SOCKET) + (Port - (NUMBER_PORTS_PER_SOCKET * IioIndex))) - 1;
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if (IioGlobalData->SetupData.VMDPortEnable[VmdPort]){
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IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] = VMD_OWNERSHIP;
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}
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} else {
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DEBUG((DEBUG_INFO, "IioGlobalData->SetupData.PcieAICEnabled[%x] = %x\n",Stack, IioGlobalData->SetupData.PcieAICEnabled[Stack]));
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//
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// Check if Pcie AIC Card will be present on Pcie Root Port
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//
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if(IioGlobalData->SetupData.PcieAICEnabled[Stack]){
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//
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// Force to have this port enabled by default for hot-plug.
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//
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IioGlobalData->SetupData.PciePortDisable[(IioIndex * NUMBER_PORTS_PER_SOCKET) + Port] = ENABLE;
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IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] = PCIEAIC_OCL_OWNERSHIP;
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DEBUG((DEBUG_ERROR, "Port = %x, PciePortDisable = %x\n",Port,IioGlobalData->SetupData.PciePortDisable[(IioIndex * NUMBER_PORTS_PER_SOCKET) + Port]));
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}
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} // No _VMD Ownership
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DEBUG((DEBUG_INFO, "PciePortOwnerShip[%x] = %x\n",Port, IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port]));
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// if PcieSSDSupport required do slot override settings accordingly
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if((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] != REGULAR_PCIE_OWNERSHIP) &&
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(SlotImplemented(IioGlobalData, Port) == TRUE)){
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IioGlobalData->SetupData.SLOTIMP[Port]= SLT_IMP;
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IioGlobalData->SetupData.SLOTPSP[Port]= 0x50 + Port; // Just program a value for PCIEACI_OCL/VMD
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IioGlobalData->SetupData.SLOTEIP[Port]= DISABLE;
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if (Slot[Index].SlotPowerLimitScale!= PWR_SCL_MAX) {
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IioGlobalData->SetupData.SLOTSPLS[Port] = Slot[Index].SlotPowerLimitScale;
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IioGlobalData->SetupData.SLOTSPLV[Port] = Slot[Index].SlotPowerLimitValue;
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}
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DEBUG((DEBUG_INFO,"Slot[Index].PcieSSDVppPort = %x\n", Slot[Index].PcieSSDVppPort));
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// Enable hot-plug if slot/port supports it
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if (Slot[Index].PcieSSDVppPort != VPP_PORT_MAX) {
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DEBUG((DEBUG_INFO, "IioGlobalData->SetupData.VMDHotPlugEnable[%x] = %x\n",Stack,IioGlobalData->SetupData.VMDHotPlugEnable[Stack]));
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DEBUG((DEBUG_INFO, "IioGlobalData->SetupData.PcieAICHotPlugEnable[%x] = %x\n",Stack,IioGlobalData->SetupData.PcieAICHotPlugEnable[Stack]));
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// Check if hot-plug is enabled for VMD or PCIeAIC case.
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if (((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] == VMD_OWNERSHIP) && (IioGlobalData->SetupData.VMDHotPlugEnable[Stack])) ||
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((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] == PCIEAIC_OCL_OWNERSHIP) && (IioGlobalData->SetupData.PcieAICHotPlugEnable[Stack]))) {
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EnableHotPlug(IioGlobalData, Port, Slot[Index].PcieSSDVppPort, Slot[Index].PcieSSDVppAddress, IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port]);
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DEBUG((DEBUG_INFO,"Enable HotPlug Done\n"));
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}
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}
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//
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// Unhide the port in order to get configured and it will be hide later for VMDLateSetup if VMD own the Pcie Root Port
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//
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IioGlobalData->SetupData.PEXPHIDE[Port]= NOT_HIDE;
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}// PcieSSDSupport
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}// PcieSSDCapable
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}// Per Slot
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}
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/**
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Auto determine which PCIe Root port to be hidden if its
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lanes are assigned to its preceding root port...use the
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Setup option variable of ConfigIOU to determine which ports
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are to be hidden on each IOU for corresponding IIO
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@param IOUx - IOUx Index
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@param IioIndex - Index to Iio
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@param IioGlobalData Pointer to Iio Globals.
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@retval None
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**/
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VOID
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CalculatePEXPHideFromIouBif (
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IN UINT8 Iou,
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IN UINT8 IioIndex,
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IN OUT IIO_GLOBALS *IioGlobalData
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)
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{
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UINT8 *PXPHide, *HidePEXPMenu;
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UINT8 CurrentIOUConfigValue;
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UINT8 PXPOffset;
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PXPHide = IioGlobalData->SetupData.PEXPHIDE;
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HidePEXPMenu = IioGlobalData->SetupData.HidePEXPMenu;
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CurrentIOUConfigValue =0;
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PXPOffset=IioIndex * NUMBER_PORTS_PER_SOCKET;
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switch (Iou) {
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case Iio_Iou0:
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CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigIOU0[IioIndex];
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PXPOffset+= PORT_1A_INDEX;
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break;
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case Iio_Iou1:
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CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigIOU1[IioIndex];
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PXPOffset+= PORT_2A_INDEX;
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break;
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case Iio_Iou2:
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CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigIOU2[IioIndex];
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PXPOffset+= PORT_3A_INDEX;
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break;
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case Iio_Mcp0:
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CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigMCP0[IioIndex];
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PXPOffset+= PORT_4A_INDEX;
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break;
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case Iio_Mcp1:
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CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigMCP1[IioIndex];
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PXPOffset += PORT_5A_INDEX;
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break;
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}
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switch(CurrentIOUConfigValue){
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case IIO_BIFURCATE_xxxxxxxx:
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PXPHide[PXPOffset + Iio_PortA] = HIDE; // hide A
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PXPHide[PXPOffset + Iio_PortB] = HIDE; // hide B
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PXPHide[PXPOffset + Iio_PortC] = HIDE; // hide C
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PXPHide[PXPOffset + Iio_PortD] = HIDE; // hide D
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HidePEXPMenu[PXPOffset + Iio_PortA] = HIDE; // hide the Setup menu for A
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HidePEXPMenu[PXPOffset + Iio_PortB] = HIDE; // hide the Setup menu for B
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HidePEXPMenu[PXPOffset + Iio_PortC] = HIDE; // hide the Setup menu for C
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HidePEXPMenu[PXPOffset + Iio_PortD] = HIDE; // hide the Setup menu for D
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break;
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case IIO_BIFURCATE_x4x4xxx8:
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PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A
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PXPHide[PXPOffset + Iio_PortB] = HIDE; // hide B
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PXPHide[PXPOffset + Iio_PortC] = NOT_HIDE; // show C
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PXPHide[PXPOffset + Iio_PortD] = NOT_HIDE; // show D
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HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for B
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HidePEXPMenu[PXPOffset + Iio_PortB] = HIDE; // hide the Setup menu for B
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HidePEXPMenu[PXPOffset + Iio_PortC] = NOT_HIDE; // show the Setup menu for D
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HidePEXPMenu[PXPOffset + Iio_PortD] = NOT_HIDE; // show the Setup menu for B
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break;
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case IIO_BIFURCATE_xxx8x4x4:
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PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A
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PXPHide[PXPOffset + Iio_PortB] = NOT_HIDE; // show B
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PXPHide[PXPOffset + Iio_PortC] = NOT_HIDE; // show C
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PXPHide[PXPOffset + Iio_PortD] = HIDE; // hide port D
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HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for A
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HidePEXPMenu[PXPOffset + Iio_PortB] = NOT_HIDE; // show the Setup menu for B
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HidePEXPMenu[PXPOffset + Iio_PortC] = NOT_HIDE; // show the Setup menu for C
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HidePEXPMenu[PXPOffset + Iio_PortD] = HIDE; // hide the Setup menu for D
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break;
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case IIO_BIFURCATE_xxx8xxx8:
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PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A
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PXPHide[PXPOffset + Iio_PortB] = HIDE; // hide B
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PXPHide[PXPOffset + Iio_PortC] = NOT_HIDE; // show C
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PXPHide[PXPOffset + Iio_PortD] = HIDE; // hide D
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HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for A
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HidePEXPMenu[PXPOffset + Iio_PortB] = HIDE; // hide the Setup menu for B
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HidePEXPMenu[PXPOffset + Iio_PortC] = NOT_HIDE; // show the Setup menu for C
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HidePEXPMenu[PXPOffset + Iio_PortD] = HIDE; // hide the Setup menu for D
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break;
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case IIO_BIFURCATE_xxxxxx16:
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PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A
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PXPHide[PXPOffset + Iio_PortB] = HIDE; // hide B
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PXPHide[PXPOffset + Iio_PortC] = HIDE; // hide C
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PXPHide[PXPOffset + Iio_PortD] = HIDE; // hide D
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HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for A
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HidePEXPMenu[PXPOffset + Iio_PortB] = HIDE; // hide the Setup menu for B
|
HidePEXPMenu[PXPOffset + Iio_PortC] = HIDE; // hide the Setup menu for C
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HidePEXPMenu[PXPOffset + Iio_PortD] = HIDE; // hide the Setup menu for D
|
break;
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default:
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PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A
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PXPHide[PXPOffset + Iio_PortB] = NOT_HIDE; // show B
|
PXPHide[PXPOffset + Iio_PortC] = NOT_HIDE; // show C
|
PXPHide[PXPOffset + Iio_PortD] = NOT_HIDE; // show port D
|
HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for A
|
HidePEXPMenu[PXPOffset + Iio_PortB] = NOT_HIDE; // show the Setup menu for B
|
HidePEXPMenu[PXPOffset + Iio_PortC] = NOT_HIDE; // show the Setup menu for C
|
HidePEXPMenu[PXPOffset + Iio_PortD] = NOT_HIDE; // show the Setup menu for D
|
break;
|
}
|
|
//
|
// Change PEXPHIDE setting to hide all PCIe port of a IOU if IIO_BIFURCATE_xxxxxxxx is set.
|
// And set ConfigIOUx/ConfigMCPx to default bifucation control value
|
// Bifurcation_Control[2:0] in IOU Bifurcation Control (PCIE_IOU_BIF_CTRL) register should be 000b ~ 100b.
|
//
|
if (CurrentIOUConfigValue == IIO_BIFURCATE_xxxxxxxx) {
|
switch (Iou) {
|
case Iio_Iou0:
|
IioGlobalData->SetupData.ConfigIOU0[IioIndex] = IIO_BIFURCATE_x4x4x4x4;
|
break;
|
case Iio_Iou1:
|
IioGlobalData->SetupData.ConfigIOU1[IioIndex] = IIO_BIFURCATE_x4x4x4x4;
|
break;
|
case Iio_Iou2:
|
IioGlobalData->SetupData.ConfigIOU2[IioIndex] = IIO_BIFURCATE_x4x4x4x4;
|
break;
|
case Iio_Mcp0:
|
IioGlobalData->SetupData.ConfigMCP0[IioIndex] = IIO_BIFURCATE_x4x4x4x4;
|
break;
|
case Iio_Mcp1:
|
IioGlobalData->SetupData.ConfigMCP1[IioIndex] = IIO_BIFURCATE_x4x4x4x4;
|
break;
|
default:
|
break;
|
}
|
}
|
}
|
|
|
VOID
|
DumpPort(
|
IIO_GLOBALS *IioGlobalData,
|
UINT8 Port,
|
UINT8 NumberOfPorts
|
)
|
{
|
UINT8 Index;
|
DEBUG((EFI_D_INFO, "IDX, Port Hide, Slot Impl, Slot Number, HotPlug, PcieSSD, VppPort, VppAddress, Interlock\n"));
|
for (Index = Port; Index < (Port + NumberOfPorts); Index++ ) {
|
DEBUG((EFI_D_INFO, "%3d| %2d | %2d | %3d | %3d | %3d | 0x%02x | 0x%02x | %2d \n", \
|
Index, \
|
IioGlobalData->SetupData.PEXPHIDE[Index], \
|
IioGlobalData->SetupData.SLOTIMP[Index], \
|
IioGlobalData->SetupData.SLOTPSP[Index], \
|
IioGlobalData->SetupData.SLOTHPCAP[Index], \
|
IioGlobalData->IioVar.IioOutData.PciePortOwnership[Index], \
|
IioGlobalData->SetupData.VppPort[Index], \
|
IioGlobalData->SetupData.VppAddress[Index],\
|
IioGlobalData->SetupData.SLOTEIP[Index]));
|
}
|
}
|
/// Dump iio configuration. Dump the current IIO configuration to the serial
|
/// log.
|
VOID
|
DumpIioConfiguration(
|
IN UINT8 iio,
|
IN IIO_GLOBALS *IioGlobalData
|
)
|
{
|
UINT8 Iou;
|
UINT8 PortIndex;
|
UINT8 Bifurcation;
|
UINT8 IouPorts;
|
PortIndex = iio * NUMBER_PORTS_PER_SOCKET;
|
/// First dump the socket number;
|
DEBUG((EFI_D_INFO, "Socket number: %d \n", iio));
|
|
/// Dump DMI configuration:
|
if ((iio == 0) && (PortIndex == 0)){
|
DEBUG((EFI_D_INFO, "PORT 0: DMI Port\n"));
|
} else {
|
DEBUG((EFI_D_INFO, "PORT 0: DMI Port working as PCIE\n"));
|
DumpPort(IioGlobalData, PortIndex, 1);
|
}
|
IouPorts=4;
|
/// Dump IOU bifurcations:
|
for (Iou = Iio_Iou0; Iou< Iio_IouMax; Iou ++) {
|
/// Reset port index.
|
PortIndex = iio * NUMBER_PORTS_PER_SOCKET;
|
// Get the bifurcation
|
switch (Iou) {
|
case Iio_Iou0:
|
Bifurcation = IioGlobalData->SetupData.ConfigIOU0[iio];
|
PortIndex += PORT_1A_INDEX;
|
DEBUG((EFI_D_INFO, "IUO0: Root Port 1, Bifurcation: %d\n", Bifurcation));
|
break;
|
case Iio_Iou1:
|
Bifurcation = IioGlobalData->SetupData.ConfigIOU1[iio];
|
PortIndex += PORT_2A_INDEX;
|
DEBUG((EFI_D_INFO, "IUO1: Root Port 2, Bifurcation: %d\n", Bifurcation));
|
break;
|
case Iio_Iou2:
|
Bifurcation = IioGlobalData->SetupData.ConfigIOU2[iio];
|
PortIndex += PORT_3A_INDEX;
|
DEBUG((EFI_D_INFO, "IUO2: Root Port 3, Bifurcation: %d\n", Bifurcation));
|
break;
|
case Iio_Mcp0:
|
Bifurcation = IioGlobalData->SetupData.ConfigMCP0[iio];
|
PortIndex += PORT_4A_INDEX;
|
DEBUG((EFI_D_INFO, "MCP0, Bifurcation: %d\n", Bifurcation));
|
break;
|
case Iio_Mcp1:
|
Bifurcation = IioGlobalData->SetupData.ConfigMCP1[iio];
|
PortIndex += PORT_5A_INDEX;
|
DEBUG((EFI_D_INFO, "MCP1, Bifurcation: %d\n", Bifurcation));
|
break;
|
default:
|
DEBUG((EFI_D_INFO, "Iou no detected = %d",Iou));
|
break;
|
}
|
DumpPort(IioGlobalData, PortIndex, IouPorts);
|
}
|
|
}
|
|
UINT8
|
GetUplinkPortInformationCommon (
|
IN UINT8 IioIndex
|
)
|
{
|
UINT8 UplinkPortIndex = 0xFF;
|
|
if (IioIndex == 0) {
|
UplinkPortIndex = PcdGet8(PcdOemSkuUplinkPortIndex);
|
}
|
|
return UplinkPortIndex;
|
}
|
/**
|
|
SystemIioPortBifurcationInit - Program the UDS data structure with OEM IIO init values
|
for SLOTs and Bifurcation.
|
|
@param mSB - pointer to this protocol
|
@param IioUds - Pointer to the IIO UDS datastructure.
|
|
@retval EFI_SUCCESS
|
|
**/
|
VOID
|
SystemIioPortBifurcationInitCommon (
|
IIO_GLOBALS *IioGlobalData,
|
IIO_BIFURCATION_ENTRY **BifurcationTable,
|
UINT8 *BifurcationEntries,
|
IIO_SLOT_CONFIG_ENTRY **SlotTable,
|
UINT8 *SlotEntries
|
)
|
{
|
|
UINT8 PortIndex;//, iio;
|
|
/// This function outline:
|
//// 1 Based on platform apply the default bifurcation and slot configuration.
|
//// 2 Apply dynamic overrides based on GPIO and other configurations.
|
//// 3 Hide unused ports due bifurcation.
|
|
for (PortIndex = 0; PortIndex < MAX_SOCKET*NUMBER_PORTS_PER_SOCKET; PortIndex++) {
|
IioGlobalData->SetupData.PEXPHIDE[PortIndex] = 0;
|
IioGlobalData->SetupData.HidePEXPMenu[PortIndex] = 0;
|
}
|
|
*BifurcationEntries = 0;
|
*SlotEntries = 0;
|
|
*BifurcationTable = (IIO_BIFURCATION_ENTRY *)(UINTN)PcdGet64 (PcdIioBifurcationTable);
|
*BifurcationEntries = PcdGet8 (PcdIioBifurcationTableEntries);
|
*SlotTable = (IIO_SLOT_CONFIG_ENTRY *)(UINTN)PcdGet64 (PcdIioSlotTable);
|
*SlotEntries = PcdGet8 (PcdIioSlotTableEntries);
|
}
|
|
VOID
|
SystemHideIioPortsCommon(
|
IIO_GLOBALS *IioGlobalData,
|
UINT8 IioIndex
|
)
|
{
|
CalculatePEXPHideFromIouBif(Iio_Iou0, IioIndex, IioGlobalData);
|
CalculatePEXPHideFromIouBif(Iio_Iou1, IioIndex, IioGlobalData);
|
CalculatePEXPHideFromIouBif(Iio_Iou2, IioIndex, IioGlobalData);
|
CalculatePEXPHideFromIouBif(Iio_Mcp0, IioIndex, IioGlobalData);
|
CalculatePEXPHideFromIouBif(Iio_Mcp1, IioIndex, IioGlobalData);
|
DumpIioConfiguration(IioIndex, IioGlobalData);
|
}
|
