/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2021, American Megatrends International LLC.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __SETUP_VARIABLE_H__
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#define __SETUP_VARIABLE_H__
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#include "UncoreCommonIncludes.h"
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// ---------------------------------------------------------------------------
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//
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// Driver Configuration
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//
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// ---------------------------------------------------------------------------
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//
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#define MAX_PCH_PCI_EXPRESS_ROOT_PORTS 8
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#define PASSWORD_MAX_SIZE 16
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#define SHA256_DIGEST_LENGTH 32
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#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002
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#pragma pack(1)
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typedef struct {
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UINT8 UserPassword[SHA256_DIGEST_LENGTH];
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UINT8 AdminPassword[SHA256_DIGEST_LENGTH];
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UINT8 Access;
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//
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// Keyboard
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//
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UINT8 Numlock;
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UINT8 Ps2PortSwap;
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//
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// TPM
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//
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UINT8 TpmEnable;
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UINT8 TpmState;
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UINT8 MorState;
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//
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// XmlCli
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//
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UINT8 XmlCliSupport;
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UINT8 SkipXmlComprs;
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UINT8 PublishSetupPgPtr;
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//
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// Breakpoints
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//
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UINT8 ValidationBreakpointType;
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UINT16 bsdBreakpoint;
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//
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// Power State
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//
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UINT8 PowerState;
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//
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// Wake On Lan
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//
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UINT8 WakeOnLanS5;
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//
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// Boot from Network
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//
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UINT8 BootNetwork;
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//
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// Video
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//
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UINT8 VideoSelect;
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UINT8 EfiWindowsInt10Workaround;
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UINT8 UefiOptimizedBootToggle;
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//
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// Fan PWM Offset
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//
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UINT8 FanPwmOffset;
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//
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// PCI Minimum Secondary Bus Number
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//
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UINT8 PCIe_MultiSeg_Support;
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//
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UINT8 WakeOnLanSupport;
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//
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// Enable/disable for PCIe LOM by using GPO44/45
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// NOT PCH LAN
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//
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UINT8 LomDisableByGpio;
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UINT8 FpkPortConfig[4];
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UINT8 FpkPortConfigPrev[4];
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UINT8 FpkPortPresent[4];
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// RTC WAKE
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//
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UINT8 WakeOnRTCS4S5;
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UINT8 RTCWakeupTimeHour;
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UINT8 RTCWakeupTimeMinute;
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UINT8 RTCWakeupTimeSecond;
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// PCI_EXPRESS_CONFIG, ROOT PORTS
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//
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// AJW: these cross the line, but depend on Platform Info
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UINT8 PcieClockGating;
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UINT8 PcieDmiAspm;
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UINT8 PcieSBDE;
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UINT8 GbePciePortNum;
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UINT8 PciePortConfig1;
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UINT8 PciePortConfig2;
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UINT8 PciePortConfig3;
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UINT8 PciePortConfig4;
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UINT8 PciePortConfig5;
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// GBE
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UINT8 GbeEnabled;
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// PCH Stepping
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UINT8 PchStepping;
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//
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// XHCI Wake On USB
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//
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UINT8 XhciWakeOnUsbEnabled;
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//
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// EventLog
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//
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//
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// SKX_TODO: add these for RAS, may be best to find new home for them in a new setup variable and setup page
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//
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UINT8 SystemErrorEn;
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//Viral, and IoMca are not supported in EP. Will need to wrap in an EX flag
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//UINT8 ViralEn;
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UINT8 PoisonEn;
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UINT8 ViralEn;
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UINT8 ClearViralStatus;
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UINT8 CloakingEn;
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UINT8 UboxToPcuMcaEn;
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UINT8 FatalErrSpinLoopEn;
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UINT8 EmcaEn;
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UINT8 EmcaIgnOptin;
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UINT8 EmcaCsmiEn;
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UINT8 EmcaMsmiEn;
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UINT8 ElogCorrErrEn;
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UINT8 ElogMemErrEn;
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UINT8 ElogProcErrEn;
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UINT8 LmceEn;
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UINT8 WheaSupportEn;
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UINT8 WheaLogMemoryEn;
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UINT8 WheaLogProcEn;
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UINT8 WheaLogPciEn;
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UINT8 WheaErrorInjSupportEn;
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UINT8 McaBankErrInjEn;
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UINT8 WheaErrInjEn;
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UINT8 WheaPcieErrInjEn;
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UINT8 MeSegErrorInjEn;
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UINT8 PcieErrInjActionTable;
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UINT8 ParityCheckEn;
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UINT8 MemErrEn;
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UINT8 CorrMemErrEn;
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UINT32 LeakyBktHiLeakyBktLo;
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UINT8 SpareIntSelect;
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UINT8 FnvErrorEn;
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UINT8 FnvErrorLowPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3 - BOTH
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UINT8 FnvErrorHighPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3 - BOTH
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UINT8 Reserved_1;
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UINT8 Reserved_2;
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UINT8 Reserved_3;
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UINT8 IioErrorEn;
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UINT8 IoMcaEn;
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UINT8 IioErrRegistersClearEn;
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UINT8 IioErrorPinEn;
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UINT8 LerEn;
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UINT8 DisableMAerrorLoggingDueToLER;
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UINT8 IioIrpErrorEn;
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UINT8 IioMiscErrorEn;
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UINT8 IioVtdErrorEn;
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UINT8 IioDmaErrorEn;
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UINT8 IioDmiErrorEn;
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UINT8 IioPcieAddCorrErrorEn;
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UINT8 IioPcieAddUnCorrEn;
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UINT8 IioPcieAerSpecCompEn;
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UINT8 PcieErrEn;
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UINT8 PcieCorrErrEn;
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UINT8 PcieUncorrErrEn;
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UINT8 PcieFatalErrEn;
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UINT8 PcieCorErrCntr;
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UINT8 PcieCorErrMaskBitMap;
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UINT16 PcieCorErrThres;
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UINT8 PcieAerCorrErrEn;
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UINT8 PcieAerAdNfatErrEn;
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UINT8 PcieAerNfatErrEn;
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UINT8 PcieAerFatErrEn;
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UINT8 SerrPropEn;
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UINT8 PerrPropEn;
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UINT8 OsSigOnSerrEn;
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UINT8 OsSigOnPerrEn;
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UINT8 CaterrGpioSmiEn;
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// Endof RAS add
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//Viral, and IoMca are not supported in EP. Will need to wrap in an EX flag
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//UINT8 IoMcaEn;
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UINT8 McBankWarmBootClearError;
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UINT8 KTIFailoverSmiEn;
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UINT8 irpp0_parityError;
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UINT8 irpp0_qtOverflow;
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UINT8 irpp0_unexprsp;
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UINT8 irpp0_csraccunaligned;
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UINT8 irpp0_unceccCs1;
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UINT8 irpp0_unceccCs0;
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UINT8 irpp0_rcvdpoison;
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UINT8 irpp0_crreccCs1;
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UINT8 irpp0_crreccCs0;
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UINT8 PropagateSerr;
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UINT8 PropagatePerr;
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//
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// Boot Options
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//
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UINT8 serialDebugMsgLvl;
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UINT8 serialDebugTrace;
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UINT8 serialDebugMsgLvlTrainResults;
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UINT8 ResetOnMemMapChange;
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UINT8 ForceSetup;
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UINT8 BiosGuardEnabled;
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UINT8 BiosGuardPlatformSupported;
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UINT8 EnableAntiFlashWearout;
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UINT8 AntiFlashWearoutSupported;
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UINT8 RtoPopulateBGDirectory;
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UINT8 Use1GPageTable;
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//
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// UINT8 QuietBoot;
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//
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UINT8 FastBoot;
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//
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// Reserve Memory that is hidden from the OS.
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//
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UINT8 ReserveMem;
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UINT64 ReserveStartAddr;
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//
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// Reserve TAGEC Memory
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//
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UINT8 TagecMem;
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//Usb Configdata
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UINT8 UsbMassDevNum;
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UINT8 UsbLegacySupport;
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UINT8 UsbEmul6064;
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UINT8 UsbMassResetDelay;
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UINT8 UsbNonBoot;
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UINT8 UsbEmu1;
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UINT8 UsbEmu2;
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UINT8 UsbEmu3;
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UINT8 UsbEmu4;
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UINT8 UsbEmu5;
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UINT8 UsbEmu6;
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UINT8 UsbEmu7;
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UINT8 UsbEmu8;
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UINT8 UsbEmu9;
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UINT8 UsbEmu10;
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UINT8 UsbEmu11;
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UINT8 UsbEmu12;
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UINT8 UsbEmu13;
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UINT8 UsbEmu14;
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UINT8 UsbEmu15;
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UINT8 UsbEmu16;
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UINT8 UsbStackSupport;
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// Console Redirection
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UINT8 ConsoleRedirection;
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UINT8 FlowControl;
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UINT64 BaudRate;
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UINT8 TerminalType;
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UINT8 LegacyOsRedirection;
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UINT8 TerminalResolution;
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UINT8 DataBits;
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UINT8 Parity;
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UINT8 StopBits;
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#ifdef EFI_PCI_IOV_SUPPORT
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UINT8 SystemPageSize;
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UINT8 ARIEnable;
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UINT8 ARIForward;
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UINT8 SRIOVEnable;
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UINT8 MRIOVEnable;
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#endif
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//
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// RAS
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//
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//
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// Network setup entries - start here <><><><><>
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//
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UINT8 LegacyPxeRom;
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UINT8 EfiNetworkSupport;
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//
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// Network setup entries - end here <><><><><>
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//
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//
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// SERIALPORT BAUD RATE: Begin
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//
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UINT32 SerialBaudRate;
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//
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// SERIALPORT BAUD RATE: END
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//
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UINT8 BootAllOptions;
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UINT8 SetShellFirst;
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//
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// Overclocking related setup variables
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//
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UINT8 PlatformOCSupport;
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UINT8 FilterPll;
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UINT8 OverclockingSupport;
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UINT8 CoreMaxOcRatio;
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UINT8 CoreVoltageMode;
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UINT16 CoreVoltageOverride;
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UINT16 CoreVoltageOffset;
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UINT8 CoreVoltageOffsetPrefix;
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UINT16 CoreExtraTurboVoltage;
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//
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// OC related
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//
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UINT8 MemoryVoltage;
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UINT8 MemoryVoltageDefault;
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UINT8 tCL;
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//
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// CLR Related
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//
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UINT8 ClrMaxOcRatio;
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UINT8 ClrVoltageMode;
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UINT16 ClrVoltageOverride;
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UINT16 ClrVoltageOffset;
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UINT8 ClrVoltageOffsetPrefix;
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UINT16 ClrExtraTurboVoltage;
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//
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// Uncore Related
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//
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UINT16 UncoreVoltageOffset;
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UINT8 UncoreVoltageOffsetPrefix;
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UINT16 IoaVoltageOffset;
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UINT8 IoaVoltageOffsetPrefix;
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UINT16 IodVoltageOffset;
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UINT8 IodVoltageOffsetPrefix;
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//
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// SVID and FIVR Related
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//
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UINT8 SvidEnable;
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UINT16 SvidVoltageOverride;
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UINT8 FivrFaultsEnable;
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UINT8 FivrEfficiencyEnable;
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UINT8 SataInterfaceRAIDMode;
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UINT8 sSataInterfaceRAIDMode;
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UINT16 C01MemoryVoltage;
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UINT16 C23MemoryVoltage;
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UINT16 CpuVccInVoltage;
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UINT8 VccIoVoltage;
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UINT8 CloudProfile;
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UINT16 VariablePlatId;
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//XTU 3.0
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UINT8 FlexRatioOverrideDefault;
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UINT8 RatioLimit1Default;
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UINT8 RatioLimit2Default;
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UINT8 RatioLimit3Default;
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UINT8 RatioLimit4Default;
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UINT8 OverclockingLockDefault;
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UINT8 DdrRefClkDefault;
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UINT8 DdrRatioDefault;
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UINT8 tCLDefault;
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UINT8 tCWLDefault;
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UINT16 tFAWDefault;
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UINT16 tRASDefault;
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UINT16 tRCDefault;
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UINT8 tRCDDefault;
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UINT16 tREFIDefault;
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UINT16 tRFCDefault;
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UINT8 tRPDefault;
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UINT8 tRPabDefault;
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UINT8 tRRDDefault;
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UINT8 tRTPDefault;
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UINT8 tWRDefault;
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UINT8 tWTRDefault;
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UINT8 NModeDefault;
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UINT8 CoreMaxOcRatioDefault;
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UINT8 CoreVoltageModeDefault;
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UINT16 CoreVoltageOverrideDefault;
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UINT16 CoreVoltageOffsetDefault;
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UINT8 CoreVoltageOffsetPrefixDefault;
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UINT16 CoreExtraTurboVoltageDefault;
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UINT8 GtOcSupportDefault;
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UINT8 GtOcFrequencyDefault;
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UINT16 GtExtraTurboVoltageDefault;
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UINT16 GtOcVoltageDefault;
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UINT8 GtVoltageModeDefault;
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UINT16 GtVoltageOverrideDefault;
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UINT16 GtVoltageOffsetDefault;
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UINT8 GtVoltageOffsetPrefixDefault;
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UINT8 ClrMaxOcRatioDefault;
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UINT8 ClrVoltageModeDefault;
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UINT16 ClrVoltageOverrideDefault;
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UINT16 ClrVoltageOffsetDefault;
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UINT8 ClrVoltageOffsetPrefixDefault;
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UINT16 ClrExtraTurboVoltageDefault;
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UINT16 UncoreVoltageOffsetDefault;
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UINT8 UncoreVoltageOffsetPrefixDefault;
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UINT16 IoaVoltageOffsetDefault;
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UINT8 IoaVoltageOffsetPrefixDefault;
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UINT16 IodVoltageOffsetDefault;
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UINT8 IodVoltageOffsetPrefixDefault;
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UINT8 SvidEnableDefault;
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UINT16 SvidVoltageOverrideDefault;
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UINT8 FivrFaultsEnableDefault;
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UINT8 FivrEfficiencyEnableDefault;
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UINT16 VrCurrentLimitDefault;
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UINT8 EnableGvDefault;
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UINT8 TurboModeDefault;
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UINT8 PowerLimit1TimeDefault;
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UINT16 PowerLimit1Default;
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UINT16 PowerLimit2Default;
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UINT8 RatioLimit1; //ratiolimit handling has changed in SKX. knobs might need to change too. Will have to revisit again.
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UINT8 RatioLimit2;
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UINT8 RatioLimit3;
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UINT8 RatioLimit4;
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UINT8 CpuRatio; // need to understand what is the difference between maxnonturboratio and cpuratio. if cpuratiooverride is 0, then cpuratio is same as maxnonturboratio. add this to platform cpu policy or socketsetup.
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UINT8 CpuRatioOverride;
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UINT8 IsTurboRatioDefaultsInitalized; // related to initializing all the vardefault. is this flow needed for HEDT/intended only for clients? no need for set up creation.
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UINT8 DdrRefClk; //cant find any in purley. new one?
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UINT8 PcieRatioDisabled;//need to check if this is applicable to HEDT. also no need to create a setup variable.
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UINT8 NMode ;
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UINT8 Pmtt;
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UINT16 GtVoltageOffset; //existing but no set up option
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UINT16 VrCurrentLimit;//done
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//UINT8 SpdProfileSelected; same as XMPMode
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UINT8 NModeSupport;
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UINT8 WDTSupportforNextOSBoot; // no setup option needed
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UINT16 TimeforNextOSBoot; // no setup optiom needed
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UINT8 PlatformUnstable; // no set up option needed. this decides if all the vardefaults are needed.
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UINT8 GtVoltageMode; //existing but no set up option
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UINT8 DdrRatio;
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UINT8 GtOcFrequency;
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UINT16 GtExtraTurboVoltage; //existing but no set up option
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UINT16 GtVoltageOverride; //existing but no set up option
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UINT8 GtVoltageOffsetPrefix;
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UINT8 GtOcSupport;
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//
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// CPU releated
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//
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UINT8 FlexOverrideEnable;
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UINT8 FlexRatioOverride;
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UINT8 PowerLimit3Override;
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UINT32 PowerLimit3;
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UINT8 PowerLimit3Time;
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UINT8 PowerLimit3DutyCycle;
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UINT8 PowerLimit3Lock;
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UINT8 MemoryVoltageOverride;
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//
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// ICC Related
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//
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UINT8 BClkOverride;
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UINT8 BclkAdjustable;
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UINT8 DmiPegRatio;
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UINT8 DfxAdvDebugJumper;
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UINT8 DfxAltPostCode;
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//
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// Validation Related
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//
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UINT8 ValidationResetType;
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UINT16 ValidationCountOuter;
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UINT16 ValidationCountInner;
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UINT8 ValidationStopOnError;
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UINT8 ValidationBootWhenDone;
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UINT8 ValidationSkxPciError;
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UINT8 ValidationSkxPciLinkError;
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UINT8 ValidationPchPciError;
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UINT8 ValidationSkxPciLinkRecoveryCountError;
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UINT16 ValidationSkxPciLinkRecoveryCountThreshold;
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UINT8 ValidationKtiError;
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UINT8 TraceHubDebugInterface;
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UINT8 RamDebugInterface;
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UINT8 StorageOpROMSuppression;
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//
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// PC_SIO_END
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//
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UINT8 RsaSupport;
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UINT8 FnvErrorMailbox; // 0 - DDRT, 1 - SMBUS
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UINT8 ReportAlertSPA; // Include SPA when reporting DDRT alert. Only to disable for MCE recovery test.
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UINT8 AEPErrorInjEn;
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UINT8 NgnHostAlertPatrolScrubUNC; // Signal DDRT interrupt upon receiving Uncorrectable Error for NGN Patrol Scrub
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UINT8 DcpmmUncPoison;
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UINT8 UCErrChkForVariableSrv;
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} SYSTEM_CONFIGURATION;
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#pragma pack()
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#define EFI_HDD_PRESENT 0x01
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#define EFI_HDD_NOT_PRESENT 0x00
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#define EFI_CD_PRESENT 0x02
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#define EFI_CD_NOT_PRESENT 0x00
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#define EFI_HDD_WARNING_ON 0x01
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#define EFI_CD_WARNING_ON 0x02
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#define EFI_SMART_WARNING_ON 0x04
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#define EFI_HDD_WARNING_OFF 0x00
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#define EFI_CD_WARNING_OFF 0x00
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#define EFI_SMART_WARNING_OFF 0x00
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#endif // #ifndef _SETUP_VARIABLE
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