/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2021, American Megatrends International LLC.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <PiPei.h>
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#include <Uefi.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/BoardInitLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/PeiServicesTablePointerLib.h>
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#include "PeiTiogaPassInitLib.h"
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#include <Ppi/BootInRecoveryMode.h>
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#include <Ppi/PchPolicy.h>
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#include <Ppi/ReadOnlyVariable2.h>
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#include <Ppi/FirmwareVolumeInfo.h>
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#include <Ppi/Reset.h>
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#include <Ppi/Smbus2.h>
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#include <Platform.h>
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#include <GpioPinsSklH.h>
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#include <Library/GpioLib.h>
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#include <Guid/SetupVariable.h>
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#include <Guid/PchRcVariable.h>
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#include <Guid/MemoryTypeInformation.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/DebugPrintErrorLevelLib.h>
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#include <Library/PrintLib.h>
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#include <SetupTable.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Platform.h>
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#include <Register/PchRegsPcr.h>
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#include <Register/PchRegsLpc.h>
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#include <Register/PchRegsSpi.h>
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#include <PchAccess.h>
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#include <Library/MmPciBaseLib.h>
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#include <IndustryStandard/Pci22.h>
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#include <Protocol/IioUds.h>
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#include <Ppi/MasterBootMode.h>
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#include <Ppi/EndOfPeiPhase.h>
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#include <Ppi/MemoryDiscovered.h>
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#include <Ppi/ReadOnlyVariable2.h>
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#include <Library/SiliconPolicyInitLib.h>
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#include <Library/SiliconPolicyUpdateLib.h>
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#include <Library/GpioLib.h>
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#include <Guid/GlobalVariable.h>
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#include <Library/TimerLib.h>
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#include <Register/PchRegsPmc.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Register/PchRegsLpc.h>
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#include <Guid/FirmwareFileSystem3.h>
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#include <Guid/SetupVariable.h>
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#include <Guid/PchRcVariable.h>
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#include <Guid/SocketVariable.h>
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#include <Library/PchPcrLib.h>
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#include <IioBifurcationSlotTable.h>
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#include <KtiHost.h>
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#include "SioRegs.h"
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#define LEGACY_8259_MASK_REGISTER_MASTER 0x21
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#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
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extern GPIO_INIT_CONFIG mGpioTableTiogaPass[];
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extern UINTN mGpioTableSizeTiogaPass;
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extern PCH_USB_OVERCURRENT_PIN Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS];
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extern PCH_USB_OVERCURRENT_PIN Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS];
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extern IIO_BIFURCATION_ENTRY mIioBifurcationTable[];
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extern UINT8 mIioBifurcationTableEntries;
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extern IIO_SLOT_CONFIG_ENTRY mIioSlotTable[];
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extern UINT8 mIioSlotTableEntries;
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extern ALL_LANES_EPARAM_LINK_INFO KtiTiogaPassAllLanesEparamTable[];
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extern UINT32 KtiTiogaPassAllLanesEparamTableSize;
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/**
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Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers.
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@param PeiServices - PeiService point.
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@param CpuIo - CpuIo PPI to read/write IO ports.
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@retval EFI_SUCCESS - Init succeed.
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**/
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VOID
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LpcSioEarlyInit (
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VOID
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)
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{
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PchLpcGenIoRangeSet ((0x600 & 0xFF0), 0x10, LPC_ESPI_FIRST_SLAVE);
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IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
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IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
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//
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//mailbox
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//
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IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE);
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IoWrite8 (SIO_DATA_PORT, SIO_MAILBOX);
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IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_HIGH0);
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IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 >> 8));
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IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_LOW0);
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IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 & 0xFF));
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//
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//active mailbox
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//
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IoWrite8 (SIO_INDEX_PORT, ACTIVATE);
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IoWrite8 (SIO_DATA_PORT, 1);
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IoWrite8 (SIO_INDEX_PORT, SIO_LOCK);
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}
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VOID
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EarlyPlatformPchInit (
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IN EFI_PEI_SERVICES **PeiServices,
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IN SYSTEM_CONFIGURATION *SystemConfiguration,
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IN PCH_RC_CONFIGURATION *PchRcConfiguration
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)
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{
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UINT16 Data16;
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UINT8 Data8;
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UINT8 TcoRebootHappened;
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UINTN SpiBaseAddress;
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UINTN P2sbBase;
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DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - Start\n"));
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SpiBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI
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);
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//
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// Program bar
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//
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P2sbBase = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_P2SB,
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PCI_FUNCTION_NUMBER_PCH_P2SB
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);
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MmioWrite32 (P2sbBase + R_PCH_P2SB_SBREG_BAR, PCH_PCR_BASE_ADDRESS);
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MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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//
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// LPC I/O Configuration
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//
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PchLpcIoDecodeRangesSet (
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(V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) |
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(V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) |
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(V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA)
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);
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PchLpcIoEnableDecodingSet (
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B_PCH_LPC_IOE_ME2 |
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B_PCH_LPC_IOE_SE |
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B_PCH_LPC_IOE_ME1 |
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B_PCH_LPC_IOE_KE |
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B_PCH_LPC_IOE_HGE |
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B_PCH_LPC_IOE_LGE |
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B_PCH_LPC_IOE_FDE |
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B_PCH_LPC_IOE_PPE |
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B_PCH_LPC_IOE_CBE |
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B_PCH_LPC_IOE_CAE,
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LPC_ESPI_FIRST_SLAVE
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);
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//
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// Enable the upper 128-byte bank of RTC RAM
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//
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PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, B_PCH_PCR_RTC_CONF_UCMOS_EN);
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//
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// Disable the Watchdog timer expiration from causing a system reset
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//
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PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~0, B_PCH_PCR_ITSS_GIC_AME);
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//
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// Halt the TCO timer
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//
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Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT);
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Data16 |= B_PCH_TCO_CNT_TMR_HLT;
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IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16);
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//
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// Read the Second TO status bit
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//
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Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS);
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DEBUG((EFI_D_ERROR, "pre read:%x\n", Data8));
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Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS);
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DEBUG((EFI_D_ERROR, "read:%x\n", Data8));
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if ((Data8 & B_PCH_TCO2_STS_SECOND_TO) == B_PCH_TCO2_STS_SECOND_TO) {
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TcoRebootHappened = 1;
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} else {
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TcoRebootHappened = 0;
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}
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if (TcoRebootHappened) {
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DEBUG ((EFI_D_ERROR, "EarlyPlatformPchInit - TCO Second TO status bit is set. This might be a TCO reboot\n"));
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}
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//
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// Clear the Second TO status bit
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//
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Data8 |= B_PCH_TCO2_STS_SECOND_TO;
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IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, Data8);
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//
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// Disable SERR NMI and IOCHK# NMI in port 61
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//
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Data8 = IoRead8 (R_PCH_NMI_SC);
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Data8 |= (B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN);
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IoWrite8 (R_PCH_NMI_SC, Data8);
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PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~B_PCH_PCR_ITSS_GIC_AME, 0);
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//
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// Clear EISS bit to allow for SPI use
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//
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MmioAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8)~B_PCH_SPI_BC_EISS);
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//
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// Disable/hide ME IDE-R device.
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//
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/*MmioWrite32(
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(MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, 0x16, 0x02) + 0x54),
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0x03
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);*/
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PchPcrAndThenOr32 (
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PID_PSF1,
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R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + R_PCH_PCR_PSFX_T0_SHDW_PCIEN,
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(UINT32)~0,
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B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS
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);
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/*MmioWrite32(
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(MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, 0x16, 0x03) + 0x54),
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0x03
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);*/
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PchPcrAndThenOr32 (
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PID_PSF1,
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R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + R_PCH_PCR_PSFX_T0_SHDW_PCIEN,
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(UINT32)~0,
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B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS
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);
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PchPcrAndThenOr32 (
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PID_PSF2,
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R_PCH_PCR_PSF2_T0_SHDW_TRH_REG_BASE + R_PCH_PCR_PSFX_T0_SHDW_PCIEN,
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(UINT32)~0,
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B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS
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);
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DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - End\n"));
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}
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/**
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Initialize POC register by Variable.
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@param *SystemConfiguration - Pointer to SystemConfiguration variables.
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@retval EFI_SUCCESS - Success.
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**/
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EFI_STATUS
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UpdatePlatformInfo (
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IN SYSTEM_CONFIGURATION *SystemConfiguration,
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IN SOCKET_CONFIGURATION *SocketConfiguration
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)
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{
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SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCoreConfig;
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SOCKET_IIO_CONFIGURATION *SocketIioConfig;
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EFI_STATUS Status;
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UINT32 PcIoApicEnable;
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#if MAX_SOCKET <= 4
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UINTN Index;
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#endif
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DEBUG((EFI_D_ERROR, "platform update platform info entry\n"));
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SocketProcessorCoreConfig = &SocketConfiguration->SocketProcessorCoreConfiguration;
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SocketIioConfig = &SocketConfiguration->IioConfig;
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#if MAX_SOCKET <= 4
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for (Index = 0; Index < 24; Index++) {
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if (SocketIioConfig->DevPresIoApicIio[Index]) {
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PcIoApicEnable |= (1 << Index);
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}
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}
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#else
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// Enable all 32 IOxAPIC
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PcIoApicEnable = 0xFFFFFFFF;
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#endif
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Status = PcdSet32S (PcdPcIoApicEnable, PcIoApicEnable);
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ASSERT_EFI_ERROR (Status);
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//
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// Check to make sure TsegSize is in range, if not use default.
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//
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if (SocketProcessorCoreConfig->TsegSize > MAX_PROCESSOR_TSEG) {
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SocketProcessorCoreConfig->TsegSize = MAX_PROCESSOR_TSEG; // if out of range make default 64M
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}
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Status = PcdSet32S (PcdMemTsegSize, (0x400000 << SocketProcessorCoreConfig->TsegSize));
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ASSERT_EFI_ERROR (Status);
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if (SocketProcessorCoreConfig->IedSize > 0) {
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Status = PcdSet32S (PcdMemIedSize, (0x400000 << (SocketProcessorCoreConfig->IedSize - 1)));
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ASSERT_EFI_ERROR (Status);
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} else {
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Status = PcdSet32S (PcdMemIedSize, 0);
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ASSERT_EFI_ERROR (Status);
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}
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//
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// Minimum SMM range in TSEG should be larger than 3M
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//
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ASSERT (PcdGet32 (PcdMemTsegSize) - PcdGet32 (PcdMemIedSize) >= 0x300000);
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return EFI_SUCCESS;
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}
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/**
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Clear any SMI status or wake status left from boot.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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ClearPchSmiAndWake (
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VOID
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)
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{
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UINT16 ABase;
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UINT16 Pm1Sts = 0;
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|
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//
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// Clear any SMI or wake state from the boot
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//
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Pm1Sts |=
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(
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B_PCH_ACPI_PM1_STS_PWRBTN
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);
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PchAcpiBaseGet (&ABase);
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//
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// Write them back
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//
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IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts);
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//
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// Clear the GPE and PM enable
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//
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IoWrite16 (ABase + R_PCH_ACPI_PM1_EN, 0);
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IoWrite32 (ABase + R_PCH_ACPI_GPE0_EN_127_96, 0);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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PlatformInitGpios (
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VOID
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)
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{
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EFI_STATUS Status;
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GPIO_INIT_CONFIG *GpioTable;
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UINTN TableSize;
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TableSize = mGpioTableSizeTiogaPass;
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DEBUG ((DEBUG_ERROR, "UBA:Size of GpioTable 0x%X, blocks: 0x%X.\n", TableSize, (TableSize/sizeof (GPIO_INIT_CONFIG)) ));
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GpioTable = mGpioTableTiogaPass;
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DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() TiogaPass Start.\n"));
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Status = GpioConfigurePads (TableSize/sizeof (GPIO_INIT_CONFIG), GpioTable);
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DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() TiogaPass End.\n"));
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return EFI_SUCCESS;
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}
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VOID
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SetUsbConfig (
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VOID
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)
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{
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EFI_STATUS Status;
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Status = PcdSet64S (PcdUsb20OverCurrentMappings, (UINT64)(UINTN)Usb20OverCurrentMappings);
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ASSERT_EFI_ERROR (Status);
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Status = PcdSet64S (PcdUsb30OverCurrentMappings, (UINT64)(UINTN)Usb30OverCurrentMappings);
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ASSERT_EFI_ERROR (Status);
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}
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VOID
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IioPortBifurcationConfig (
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VOID
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)
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{
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EFI_STATUS Status;
|
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Status = PcdSet64S (PcdIioBifurcationTable, (UINT64)(UINTN)mIioBifurcationTable);
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ASSERT_EFI_ERROR (Status);
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Status = PcdSet8S (PcdIioBifurcationTableEntries, mIioBifurcationTableEntries);
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ASSERT_EFI_ERROR (Status);
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Status = PcdSet64S (PcdIioSlotTable, (UINT64)(UINTN)mIioSlotTable);
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ASSERT_EFI_ERROR (Status);
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Status = PcdSet8S (PcdIioSlotTableEntries, mIioSlotTableEntries);
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ASSERT_EFI_ERROR (Status);
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}
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VOID
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AllLanesEparamTableConfig (
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VOID
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)
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{
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EFI_STATUS Status;
|
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Status = PcdSet64S (PcdAllLanesEparamTable, (UINT64)(UINTN)KtiTiogaPassAllLanesEparamTable);
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ASSERT_EFI_ERROR (Status);
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Status = PcdSet32S (PcdAllLanesEparamTableSize, KtiTiogaPassAllLanesEparamTableSize);
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ASSERT_EFI_ERROR (Status);
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}
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|
EFI_STATUS
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PchLanConfig (
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IN SYSTEM_CONFIGURATION *SystemConfig
|
)
|
{
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GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableByGpio);
|
|
return EFI_SUCCESS;
|
}
|
|
/**
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Write to mask registers of master and slave 8259 PICs.
|
|
**/
|
VOID
|
STATIC
|
Mask8259Interrupts (
|
VOID
|
)
|
{
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IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF);
|
IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF);
|
}
|
|
EFI_STATUS
|
EFIAPI
|
TiogaPassBoardInitBeforeMemoryInit (
|
VOID
|
)
|
{
|
EFI_STATUS Status;
|
SETUP_DATA SetupData;
|
SYSTEM_CONFIGURATION SystemConfiguration;
|
PCH_RC_CONFIGURATION PchRcConfiguration;
|
SOCKET_CONFIGURATION SocketConfiguration;
|
UINT16 ABase;
|
UINT16 Pm1Sts;
|
UINT32 Pm1Cnt;
|
CONST EFI_PEI_SERVICES ** PeiServices;
|
|
PeiServices = GetPeiServicesTablePointer ();
|
|
ZeroMem (&SetupData, sizeof(SETUP_DATA));
|
CopyMem (&SetupData.SocketConfig.IioConfig, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION));
|
CopyMem (&SetupData.SocketConfig.CommonRcConfig, PcdGetPtr(PcdSocketCommonRcConfigData), sizeof(SOCKET_COMMONRC_CONFIGURATION));
|
CopyMem (&SetupData.SocketConfig.CsiConfig, PcdGetPtr(PcdSocketMpLinkConfigData), sizeof(SOCKET_MP_LINK_CONFIGURATION));
|
CopyMem (&SetupData.SocketConfig.MemoryConfig, PcdGetPtr(PcdSocketMemoryConfigData), sizeof(SOCKET_MEMORY_CONFIGURATION));
|
CopyMem (&SetupData.SocketConfig.PowerManagementConfig, PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
|
CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, PcdGetPtr(PcdSocketProcessorCoreConfigData), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION));
|
CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetupData), sizeof(SYSTEM_CONFIGURATION));
|
CopyMem (&SetupData.PchRcConfig, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION));
|
|
CopyMem (&SocketConfiguration, &(SetupData.SocketConfig), sizeof (SOCKET_CONFIGURATION));
|
CopyMem (&PchRcConfiguration, &(SetupData.PchRcConfig), sizeof (PCH_RC_CONFIGURATION));
|
CopyMem (&SystemConfiguration, &(SetupData.SystemConfig), sizeof (SYSTEM_CONFIGURATION));
|
|
///
|
/// Set LPC SIO
|
///
|
MmioOr16(
|
(MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_IOE),
|
B_PCH_LPC_IOE_SE
|
);
|
|
LpcSioEarlyInit ();
|
|
Status = PlatformInitGpios ();
|
ASSERT_EFI_ERROR (Status);
|
|
SetUsbConfig ();
|
IioPortBifurcationConfig ();
|
AllLanesEparamTableConfig ();
|
|
///
|
/// Do Early PCH init
|
///
|
EarlyPlatformPchInit ((EFI_PEI_SERVICES**)PeiServices, &SystemConfiguration, &PchRcConfiguration);
|
|
///
|
/// Clear PCH SMI and Wake
|
/// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
|
///
|
Status = ClearPchSmiAndWake();
|
ASSERT_EFI_ERROR (Status);
|
///----------------------------------------------------------------------------------
|
///
|
/// BIOS should check the WAK_STS bit in PM1_STS[15] (PCH register ABASE+00h) before memory
|
/// initialization to determine if ME has reset the system while the host was in a sleep state.
|
/// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is taken by overwriting
|
/// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit.
|
///
|
PchAcpiBaseGet (&ABase);
|
Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS);
|
if ((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) == 0) {
|
Pm1Cnt = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT);
|
Pm1Cnt |= V_PCH_ACPI_PM1_CNT_S5;
|
IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
|
}
|
|
UpdatePlatformInfo (&SystemConfiguration, &SocketConfiguration);
|
|
//
|
// Do platform specific on-board Zoar init
|
//
|
PchLanConfig (&SystemConfiguration);
|
|
//
|
// The 8259 PIC is still functional and not masked by default even if APIC is
|
// enabled. So need to disable all 8259 interrupts.
|
//
|
Mask8259Interrupts ();
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
|
Turn off system if needed.
|
|
@param PeiServices Pointer to PEI Services
|
@param CpuIo Pointer to CPU I/O Protocol
|
|
@retval None.
|
|
**/
|
VOID
|
CheckPowerOffNow (
|
VOID
|
)
|
{
|
|
UINT16 Pm1Sts;
|
|
//
|
// Read and check the ACPI registers
|
//
|
Pm1Sts = IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_STS);
|
DEBUG ((EFI_D_ERROR, "CheckPowerOffNow()- Pm1Sts= 0x%04x\n", Pm1Sts ));
|
|
if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) == B_PCH_ACPI_PM1_STS_PWRBTN) {
|
IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);
|
IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5);
|
IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN);
|
}
|
}
|
|
EFI_STATUS
|
EFIAPI
|
TiogaPassBoardInitAfterMemoryInit (
|
VOID
|
)
|
{
|
EFI_STATUS Status;
|
EFI_BOOT_MODE BootMode;
|
UINT16 Pm1Cnt;
|
|
Status = PeiServicesGetBootMode (&BootMode);
|
ASSERT_EFI_ERROR (Status);
|
|
//
|
// Check if user wants to turn off in PEI phase
|
//
|
if (BootMode != BOOT_ON_S3_RESUME) {
|
CheckPowerOffNow ();
|
} else {
|
Pm1Cnt = IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT);
|
Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
|
IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
EFI_STATUS
|
EFIAPI
|
TiogaPassBoardDebugInit (
|
VOID
|
)
|
{
|
return EFI_SUCCESS;
|
}
|
|
EFI_BOOT_MODE
|
EFIAPI
|
TiogaPassBoardBootModeDetect (
|
VOID
|
)
|
{
|
return BOOT_WITH_FULL_CONFIGURATION;
|
}
|
|
