/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2021, American Megatrends International LLC.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/BoardInitLib.h>
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#include <Setup/IioUniversalData.h>
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#include "PeiTiogaPassInitLib.h"
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VOID
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GetIioUdsHob (
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IN IIO_UDS **UdsHobPtr
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)
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{
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EFI_GUID UniversalDataGuid = IIO_UNIVERSAL_DATA_GUID;
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EFI_HOB_GUID_TYPE *GuidHob;
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ASSERT(UdsHobPtr);
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*UdsHobPtr = NULL;
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GuidHob = GetFirstGuidHob (&UniversalDataGuid);
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if (GuidHob){
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*UdsHobPtr = GET_GUID_HOB_DATA (GuidHob);
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return;
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}
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ASSERT(FALSE);
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}
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EFI_STATUS
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EFIAPI
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TiogaPassBoardInitBeforeSiliconInit (
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VOID
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)
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{
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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TiogaPassBoardInitAfterSiliconInit (
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VOID
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)
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{
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IIO_UDS *IioUds;
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DEBUG((EFI_D_ERROR, "TiogaPassBoardInitAfterSiliconInit\n"));
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GetIioUdsHob(&IioUds);
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DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", IioUds->PlatformData.MemTolm));
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DEBUG (
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(EFI_D_ERROR,
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"PCIE BASE: %lX Size : %X\n",
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IioUds->PlatformData.PciExpressBase,
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IioUds->PlatformData.PciExpressSize)
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);
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DEBUG (
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(EFI_D_ERROR,
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"PCI32 BASE: %X Limit: %X\n",
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IioUds->PlatformData.PlatGlobalMmiolBase,
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IioUds->PlatformData.PlatGlobalMmiolLimit)
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);
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DEBUG (
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(EFI_D_ERROR,
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"PCI64 BASE: %lX Limit: %lX\n",
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IioUds->PlatformData.PlatGlobalMmiohBase,
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IioUds->PlatformData.PlatGlobalMmiohLimit)
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);
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DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", IioUds->PlatformData.PlatGlobalMmiohBase, (IioUds->PlatformData.PlatGlobalMmiohLimit + 1)));
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return EFI_SUCCESS;
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}
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