/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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Scope (\_SB) {
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Name (PR00, Package() {
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// [DMI0]: Legacy PCI Express Port 0 on PC00
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Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [CB0A]: CB3DMA on PC00
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// [CB0E]: CB3DMA on PC00
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Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [CB0B]: CB3DMA on PC00
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// [CB0F]: CB3DMA on PC00
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Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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// [CB0C]: CB3DMA on PC00
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// [CB0G]: CB3DMA on PC00
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Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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// [CB0D]: CB3DMA on PC00
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// [CB0H]: CB3DMA on PC00
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Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [IIM0]: IIOMISC on PC00
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Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [UBX0]: Uncore 0 UBOX Device
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Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [DISP]: Display Controller
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Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [IHC1]: HECI #1
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// [IHC3]: HECI #3
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Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [IHC2]: HECI #2
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Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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// [IIDR]: IDE-Redirection (IDE-R)
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Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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// [IMKT]: Keyboard and Text (KT) Redirection
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Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [SAT2]: sSATA Host controller 2 on PCH
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Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [XHCI]: xHCI controller 1 on PCH
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Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [OTG0]: USB Device Controller (OTG) on PCH
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Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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// [TERM]: Thermal Subsystem on PCH
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Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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// [CAMR]: Camera IO Host Controller on PCH
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Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [HEC1]: HECI #1 on PCH
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// [HEC3]: HECI #3 on PCH
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Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [HEC2]: HECI #2 on PCH
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Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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// [IDER]: ME IDE redirect on PCH
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Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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// [MEKT]: MEKT on PCH
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Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [SAT1]: SATA controller 1 on PCH
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Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [NAN1]: NAND Cycle Router on PCH
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Package() { 0x0018FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [RP17]: PCIE PCH Root Port #17
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Package() { 0x001BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [RP18]: PCIE PCH Root Port #18
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Package() { 0x001BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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// [RP19]: PCIE PCH Root Port #19
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Package() { 0x001BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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// [RP20]: PCIE PCH Root Port #20
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Package() { 0x001BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [RP01]: PCIE PCH Root Port #1
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// [RP05]: PCIE PCH Root Port #5
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Package() { 0x001CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [RP02]: PCIE PCH Root Port #2
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// [RP06]: PCIE PCH Root Port #6
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Package() { 0x001CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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// [RP03]: PCIE PCH Root Port #3
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// [RP07]: PCIE PCH Root Port #7
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Package() { 0x001CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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// [RP04]: PCIE PCH Root Port #4
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// [RP08]: PCIE PCH Root Port #8
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Package() { 0x001CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [RP09]: PCIE PCH Root Port #9
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// [RP13]: PCIE PCH Root Port #13
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Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [RP10]: PCIE PCH Root Port #10
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// [RP14]: PCIE PCH Root Port #14
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Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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// [RP11]: PCIE PCH Root Port #11
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// [RP15]: PCIE PCH Root Port #15
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Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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// [RP12]: PCIE PCH Root Port #12
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// [RP16]: PCIE PCH Root Port #16
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Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [UAR0]: UART #0 on PCH
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Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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// [UAR1]: UART #1 on PCH
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Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
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// [SPI0]: SPI #0 on PCH
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Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
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// [SPI1]: SPI #1 on PCH
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Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
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// [CAVS]: HD Audio Subsystem Controller on PCH
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// [SMBS]: SMBus controller on PCH
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// [GBE1]: GbE Controller on PCH
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// [NTPK]: Northpeak Controller on PCH
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Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
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})
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Name (AR00, Package() {
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// [DMI0]: Legacy PCI Express Port 0 on PC00
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Package() { 0x0000FFFF, 0, 0, 16 },
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// [CB0A]: CB3DMA on PC00
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// [CB0E]: CB3DMA on PC00
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Package() { 0x0004FFFF, 0, 0, 16 },
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// [CB0B]: CB3DMA on PC00
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// [CB0F]: CB3DMA on PC00
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Package() { 0x0004FFFF, 1, 0, 17 },
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// [CB0C]: CB3DMA on PC00
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// [CB0G]: CB3DMA on PC00
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Package() { 0x0004FFFF, 2, 0, 18 },
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// [CB0D]: CB3DMA on PC00
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// [CB0H]: CB3DMA on PC00
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Package() { 0x0004FFFF, 3, 0, 19 },
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// [IIM0]: IIOMISC on PC00
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Package() { 0x0005FFFF, 0, 0, 16 },
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Package() { 0x0005FFFF, 1, 0, 17 },
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Package() { 0x0005FFFF, 2, 0, 18 },
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Package() { 0x0005FFFF, 3, 0, 19 },
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// [UBX0]: Uncore 0 UBOX Device
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Package() { 0x0008FFFF, 0, 0, 16 },
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Package() { 0x0008FFFF, 1, 0, 17 },
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Package() { 0x0008FFFF, 2, 0, 18 },
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Package() { 0x0008FFFF, 3, 0, 19 },
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// [DISP]: Display Controller
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Package() { 0x000FFFFF, 0, 0, 16 },
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// [IHC1]: HECI #1
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// [IHC3]: HECI #3
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Package() { 0x0010FFFF, 0, 0, 16 },
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// [IHC2]: HECI #2
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Package() { 0x0010FFFF, 1, 0, 17 },
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// [IIDR]: IDE-Redirection (IDE-R)
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Package() { 0x0010FFFF, 2, 0, 18 },
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// [IMKT]: Keyboard and Text (KT) Redirection
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Package() { 0x0010FFFF, 3, 0, 19 },
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// [SAT2]: sSATA Host controller 2 on PCH
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Package() { 0x0011FFFF, 0, 0, 16 },
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// [XHCI]: xHCI controller 1 on PCH
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Package() { 0x0014FFFF, 0, 0, 16 },
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// [OTG0]: USB Device Controller (OTG) on PCH
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Package() { 0x0014FFFF, 1, 0, 17 },
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// [TERM]: Thermal Subsystem on PCH
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Package() { 0x0014FFFF, 2, 0, 18 },
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// [CAMR]: Camera IO Host Controller on PCH
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Package() { 0x0014FFFF, 3, 0, 19 },
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// [HEC1]: HECI #1 on PCH
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// [HEC3]: HECI #3 on PCH
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Package() { 0x0016FFFF, 0, 0, 16 },
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// [HEC2]: HECI #2 on PCH
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Package() { 0x0016FFFF, 1, 0, 17 },
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// [IDER]: ME IDE redirect on PCH
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Package() { 0x0016FFFF, 2, 0, 18 },
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// [MEKT]: MEKT on PCH
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Package() { 0x0016FFFF, 3, 0, 19 },
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// [SAT1]: SATA controller 1 on PCH
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Package() { 0x0017FFFF, 0, 0, 16 },
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// [NAN1]: NAND Cycle Router on PCH
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Package() { 0x0018FFFF, 0, 0, 16 },
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// [RP17]: PCIE PCH Root Port #17
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Package() { 0x001BFFFF, 0, 0, 16 },
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// [RP18]: PCIE PCH Root Port #18
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Package() { 0x001BFFFF, 1, 0, 17 },
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// [RP19]: PCIE PCH Root Port #19
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Package() { 0x001BFFFF, 2, 0, 18 },
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// [RP20]: PCIE PCH Root Port #20
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Package() { 0x001BFFFF, 3, 0, 19 },
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// [RP01]: PCIE PCH Root Port #1
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// [RP05]: PCIE PCH Root Port #5
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Package() { 0x001CFFFF, 0, 0, 16 },
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// [RP02]: PCIE PCH Root Port #2
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// [RP06]: PCIE PCH Root Port #6
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Package() { 0x001CFFFF, 1, 0, 17 },
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// [RP03]: PCIE PCH Root Port #3
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// [RP07]: PCIE PCH Root Port #7
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Package() { 0x001CFFFF, 2, 0, 18 },
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// [RP04]: PCIE PCH Root Port #4
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// [RP08]: PCIE PCH Root Port #8
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Package() { 0x001CFFFF, 3, 0, 19 },
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// [RP09]: PCIE PCH Root Port #9
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// [RP13]: PCIE PCH Root Port #13
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Package() { 0x001DFFFF, 0, 0, 16 },
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// [RP10]: PCIE PCH Root Port #10
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// [RP14]: PCIE PCH Root Port #14
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Package() { 0x001DFFFF, 1, 0, 17 },
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// [RP11]: PCIE PCH Root Port #11
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// [RP15]: PCIE PCH Root Port #15
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Package() { 0x001DFFFF, 2, 0, 18 },
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// [RP12]: PCIE PCH Root Port #12
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// [RP16]: PCIE PCH Root Port #16
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Package() { 0x001DFFFF, 3, 0, 19 },
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// [UAR0]: UART #0 on PCH
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Package() { 0x001EFFFF, 0, 0, 20 },
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// [UAR1]: UART #1 on PCH
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Package() { 0x001EFFFF, 1, 0, 21 },
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// [SPI0]: SPI #0 on PCH
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Package() { 0x001EFFFF, 2, 0, 22 },
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// [SPI1]: SPI #1 on PCH
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Package() { 0x001EFFFF, 3, 0, 23 },
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// [CAVS]: HD Audio Subsystem Controller on PCH
|
// [SMBS]: SMBus controller on PCH
|
// [GBE1]: GbE Controller on PCH
|
// [NTPK]: Northpeak Controller on PCH
|
Package() { 0x001FFFFF, 0, 0, 16 },
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})
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Name (AH00, Package() {
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// [DMI0]: Legacy PCI Express Port 0 on PC00
|
Package() { 0x0000FFFF, 0, 0, 31 },
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// [CB0A]: CB3DMA on PC00
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// [CB0E]: CB3DMA on PC00
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Package() { 0x0004FFFF, 0, 0, 26 },
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// [CB0B]: CB3DMA on PC00
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// [CB0F]: CB3DMA on PC00
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Package() { 0x0004FFFF, 1, 0, 27 },
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// [CB0C]: CB3DMA on PC00
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// [CB0G]: CB3DMA on PC00
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Package() { 0x0004FFFF, 2, 0, 26 },
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// [CB0D]: CB3DMA on PC00
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// [CB0H]: CB3DMA on PC00
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Package() { 0x0004FFFF, 3, 0, 27 },
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// [IIM0]: IIOMISC on PC00
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Package() { 0x0005FFFF, 0, 0, 16 },
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Package() { 0x0005FFFF, 1, 0, 17 },
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Package() { 0x0005FFFF, 2, 0, 18 },
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Package() { 0x0005FFFF, 3, 0, 19 },
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// [UBX0]: Uncore 0 UBOX Device
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Package() { 0x0008FFFF, 0, 0, 24 },
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Package() { 0x0008FFFF, 1, 0, 28 },
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Package() { 0x0008FFFF, 2, 0, 29 },
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Package() { 0x0008FFFF, 3, 0, 30 },
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// [DISP]: Display Controller
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Package() { 0x000FFFFF, 0, 0, 16 },
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// [IHC1]: HECI #1
|
// [IHC3]: HECI #3
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Package() { 0x0010FFFF, 0, 0, 16 },
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// [IHC2]: HECI #2
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Package() { 0x0010FFFF, 1, 0, 17 },
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// [IIDR]: IDE-Redirection (IDE-R)
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Package() { 0x0010FFFF, 2, 0, 18 },
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// [IMKT]: Keyboard and Text (KT) Redirection
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Package() { 0x0010FFFF, 3, 0, 19 },
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// [SAT2]: sSATA Host controller 2 on PCH
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Package() { 0x0011FFFF, 0, 0, 16 },
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// [XHCI]: xHCI controller 1 on PCH
|
Package() { 0x0014FFFF, 0, 0, 16 },
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// [OTG0]: USB Device Controller (OTG) on PCH
|
Package() { 0x0014FFFF, 1, 0, 17 },
|
// [TERM]: Thermal Subsystem on PCH
|
Package() { 0x0014FFFF, 2, 0, 18 },
|
// [CAMR]: Camera IO Host Controller on PCH
|
Package() { 0x0014FFFF, 3, 0, 19 },
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// [HEC1]: HECI #1 on PCH
|
// [HEC3]: HECI #3 on PCH
|
Package() { 0x0016FFFF, 0, 0, 16 },
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// [HEC2]: HECI #2 on PCH
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
// [IDER]: ME IDE redirect on PCH
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
// [MEKT]: MEKT on PCH
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [SAT1]: SATA controller 1 on PCH
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
// [NAN1]: NAND Cycle Router on PCH
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Package() { 0x0018FFFF, 0, 0, 16 },
|
// [RP17]: PCIE PCH Root Port #17
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Package() { 0x001BFFFF, 0, 0, 16 },
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// [RP18]: PCIE PCH Root Port #18
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Package() { 0x001BFFFF, 1, 0, 17 },
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// [RP19]: PCIE PCH Root Port #19
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Package() { 0x001BFFFF, 2, 0, 18 },
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// [RP20]: PCIE PCH Root Port #20
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Package() { 0x001BFFFF, 3, 0, 19 },
|
// [RP01]: PCIE PCH Root Port #1
|
// [RP05]: PCIE PCH Root Port #5
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Package() { 0x001CFFFF, 0, 0, 16 },
|
// [RP02]: PCIE PCH Root Port #2
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// [RP06]: PCIE PCH Root Port #6
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Package() { 0x001CFFFF, 1, 0, 17 },
|
// [RP03]: PCIE PCH Root Port #3
|
// [RP07]: PCIE PCH Root Port #7
|
Package() { 0x001CFFFF, 2, 0, 18 },
|
// [RP04]: PCIE PCH Root Port #4
|
// [RP08]: PCIE PCH Root Port #8
|
Package() { 0x001CFFFF, 3, 0, 19 },
|
// [RP09]: PCIE PCH Root Port #9
|
// [RP13]: PCIE PCH Root Port #13
|
Package() { 0x001DFFFF, 0, 0, 16 },
|
// [RP10]: PCIE PCH Root Port #10
|
// [RP14]: PCIE PCH Root Port #14
|
Package() { 0x001DFFFF, 1, 0, 17 },
|
// [RP11]: PCIE PCH Root Port #11
|
// [RP15]: PCIE PCH Root Port #15
|
Package() { 0x001DFFFF, 2, 0, 18 },
|
// [RP12]: PCIE PCH Root Port #12
|
// [RP16]: PCIE PCH Root Port #16
|
Package() { 0x001DFFFF, 3, 0, 19 },
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// [UAR0]: UART #0 on PCH
|
Package() { 0x001EFFFF, 0, 0, 20 },
|
// [UAR1]: UART #1 on PCH
|
Package() { 0x001EFFFF, 1, 0, 21 },
|
// [SPI0]: SPI #0 on PCH
|
Package() { 0x001EFFFF, 2, 0, 22 },
|
// [SPI1]: SPI #1 on PCH
|
Package() { 0x001EFFFF, 3, 0, 23 },
|
// [CAVS]: HD Audio Subsystem Controller on PCH
|
// [SMBS]: SMBus controller on PCH
|
// [GBE1]: GbE Controller on PCH
|
// [NTPK]: Northpeak Controller on PCH
|
Package() { 0x001FFFFF, 0, 0, 16 },
|
})
|
|
Name (PR01, Package() {
|
// [SLTH]: PCIE PCH Slot #17
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR01, Package() {
|
// [SLTH]: PCIE PCH Slot #17
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (PR02, Package() {
|
// [SLTI]: PCIE PCH Slot #18
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR02, Package() {
|
// [SLTI]: PCIE PCH Slot #18
|
Package() { 0x0000FFFF, 0, 0, 17 },
|
Package() { 0x0000FFFF, 1, 0, 18 },
|
Package() { 0x0000FFFF, 2, 0, 19 },
|
Package() { 0x0000FFFF, 3, 0, 16 },
|
})
|
|
Name (PR03, Package() {
|
// [SLTJ]: PCIE PCH Slot #19
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
|
})
|
|
Name (AR03, Package() {
|
// [SLTJ]: PCIE PCH Slot #19
|
Package() { 0x0000FFFF, 0, 0, 18 },
|
Package() { 0x0000FFFF, 1, 0, 19 },
|
Package() { 0x0000FFFF, 2, 0, 16 },
|
Package() { 0x0000FFFF, 3, 0, 17 },
|
})
|
|
Name (PR04, Package() {
|
// [SLTK]: PCIE PCH Slot #20
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
|
})
|
|
Name (AR04, Package() {
|
// [SLTK]: PCIE PCH Slot #20
|
Package() { 0x0000FFFF, 0, 0, 19 },
|
Package() { 0x0000FFFF, 1, 0, 16 },
|
Package() { 0x0000FFFF, 2, 0, 17 },
|
Package() { 0x0000FFFF, 3, 0, 18 },
|
})
|
|
Name (PR05, Package() {
|
// [SLT1]: PCIE PCH Slot #1
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR05, Package() {
|
// [SLT1]: PCIE PCH Slot #1
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (PR06, Package() {
|
// [SLT2]: PCIE PCH Slot #2
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR06, Package() {
|
// [SLT2]: PCIE PCH Slot #2
|
Package() { 0x0000FFFF, 0, 0, 17 },
|
Package() { 0x0000FFFF, 1, 0, 18 },
|
Package() { 0x0000FFFF, 2, 0, 19 },
|
Package() { 0x0000FFFF, 3, 0, 16 },
|
})
|
|
Name (PR07, Package() {
|
// [SLT3]: PCIE PCH Slot #3
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
|
})
|
|
Name (AR07, Package() {
|
// [SLT3]: PCIE PCH Slot #3
|
Package() { 0x0000FFFF, 0, 0, 18 },
|
Package() { 0x0000FFFF, 1, 0, 19 },
|
Package() { 0x0000FFFF, 2, 0, 16 },
|
Package() { 0x0000FFFF, 3, 0, 17 },
|
})
|
|
Name (PR08, Package() {
|
// [SLT4]: PCIE PCH Slot #4
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
|
})
|
|
Name (AR08, Package() {
|
// [SLT4]: PCIE PCH Slot #4
|
Package() { 0x0000FFFF, 0, 0, 19 },
|
Package() { 0x0000FFFF, 1, 0, 16 },
|
Package() { 0x0000FFFF, 2, 0, 17 },
|
Package() { 0x0000FFFF, 3, 0, 18 },
|
})
|
|
Name (PR09, Package() {
|
// [SLT5]: PCIE PCH Slot #5
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR09, Package() {
|
// [SLT5]: PCIE PCH Slot #5
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (PR0A, Package() {
|
// [SLT6]: PCIE PCH Slot #6
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR0A, Package() {
|
// [SLT6]: PCIE PCH Slot #6
|
Package() { 0x0000FFFF, 0, 0, 17 },
|
Package() { 0x0000FFFF, 1, 0, 18 },
|
Package() { 0x0000FFFF, 2, 0, 19 },
|
Package() { 0x0000FFFF, 3, 0, 16 },
|
})
|
|
Name (PR0B, Package() {
|
// [SLT7]: PCIE PCH Slot #7
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
|
})
|
|
Name (AR0B, Package() {
|
// [SLT7]: PCIE PCH Slot #7
|
Package() { 0x0000FFFF, 0, 0, 18 },
|
Package() { 0x0000FFFF, 1, 0, 19 },
|
Package() { 0x0000FFFF, 2, 0, 16 },
|
Package() { 0x0000FFFF, 3, 0, 17 },
|
})
|
|
Name (PR0C, Package() {
|
// [SLT8]: PCIE PCH Slot #8
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
|
})
|
|
Name (AR0C, Package() {
|
// [SLT8]: PCIE PCH Slot #8
|
Package() { 0x0000FFFF, 0, 0, 19 },
|
Package() { 0x0000FFFF, 1, 0, 16 },
|
Package() { 0x0000FFFF, 2, 0, 17 },
|
Package() { 0x0000FFFF, 3, 0, 18 },
|
})
|
|
Name (PR0D, Package() {
|
// [SLT9]: PCIE PCH Slot #9
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR0D, Package() {
|
// [SLT9]: PCIE PCH Slot #9
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (PR0E, Package() {
|
// [SLTA]: PCIE PCH Slot #10
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR0E, Package() {
|
// [SLTA]: PCIE PCH Slot #10
|
Package() { 0x0000FFFF, 0, 0, 17 },
|
Package() { 0x0000FFFF, 1, 0, 18 },
|
Package() { 0x0000FFFF, 2, 0, 19 },
|
Package() { 0x0000FFFF, 3, 0, 16 },
|
})
|
|
Name (PR0F, Package() {
|
// [SLTB]: PCIE PCH Slot #11
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
|
})
|
|
Name (AR0F, Package() {
|
// [SLTB]: PCIE PCH Slot #11
|
Package() { 0x0000FFFF, 0, 0, 18 },
|
Package() { 0x0000FFFF, 1, 0, 19 },
|
Package() { 0x0000FFFF, 2, 0, 16 },
|
Package() { 0x0000FFFF, 3, 0, 17 },
|
})
|
|
Name (PR10, Package() {
|
// [SLTC]: PCIE PCH Slot #12
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
|
})
|
|
Name (AR10, Package() {
|
// [SLTC]: PCIE PCH Slot #12
|
Package() { 0x0000FFFF, 0, 0, 19 },
|
Package() { 0x0000FFFF, 1, 0, 16 },
|
Package() { 0x0000FFFF, 2, 0, 17 },
|
Package() { 0x0000FFFF, 3, 0, 18 },
|
})
|
|
Name (PR11, Package() {
|
// [SLTD]: PCIE PCH Slot #13
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR11, Package() {
|
// [SLTD]: PCIE PCH Slot #13
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (PR12, Package() {
|
// [SLTE]: PCIE PCH Slot #14
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR12, Package() {
|
// [SLTE]: PCIE PCH Slot #14
|
Package() { 0x0000FFFF, 0, 0, 17 },
|
Package() { 0x0000FFFF, 1, 0, 18 },
|
Package() { 0x0000FFFF, 2, 0, 19 },
|
Package() { 0x0000FFFF, 3, 0, 16 },
|
})
|
|
Name (PR13, Package() {
|
// [SLTF]: PCIE PCH Slot #15
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
|
})
|
|
Name (AR13, Package() {
|
// [SLTF]: PCIE PCH Slot #15
|
Package() { 0x0000FFFF, 0, 0, 18 },
|
Package() { 0x0000FFFF, 1, 0, 19 },
|
Package() { 0x0000FFFF, 2, 0, 16 },
|
Package() { 0x0000FFFF, 3, 0, 17 },
|
})
|
|
Name (PR14, Package() {
|
// [SLTG]: PCIE PCH Slot #16
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
|
})
|
|
Name (AR14, Package() {
|
// [SLTG]: PCIE PCH Slot #16
|
Package() { 0x0000FFFF, 0, 0, 19 },
|
Package() { 0x0000FFFF, 1, 0, 16 },
|
Package() { 0x0000FFFF, 2, 0, 17 },
|
Package() { 0x0000FFFF, 3, 0, 18 },
|
})
|
|
Name (PR15, Package() {
|
// [BR1A]: PCI Express Port 1A on PC01
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [BR1B]: PCI Express Port 1B on PC01
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [BR1C]: PCI Express Port 1C on PC01
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [BR1D]: PCI Express Port 1D on PC01
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [CHA0]: Uncore 1 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHA1]: Uncore 1 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHA2]: Uncore 1 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHA3]: Uncore 1 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHA4]: Uncore 1 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHA5]: Uncore 1 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHA6]: Uncore 1 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHA7]: Uncore 1 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS0]: Uncore 1 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS1]: Uncore 1 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS2]: Uncore 1 CMS0CHA16-23 Device
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS3]: Uncore 1 CMS0CHA24-27 Device
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CDL0]: Uncore 1 CHASADALL Device
|
Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [PCU0]: Uncore 1 PCUCR Devices
|
Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [VCU0]: Uncore 1 VCUCR Device
|
Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR15, Package() {
|
// [BR1A]: PCI Express Port 1A on PC01
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [BR1B]: PCI Express Port 1B on PC01
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [BR1C]: PCI Express Port 1C on PC01
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [BR1D]: PCI Express Port 1D on PC01
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [CHA0]: Uncore 1 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
// [CHA1]: Uncore 1 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, 0, 16 },
|
Package() { 0x0009FFFF, 1, 0, 17 },
|
Package() { 0x0009FFFF, 2, 0, 18 },
|
Package() { 0x0009FFFF, 3, 0, 19 },
|
// [CHA2]: Uncore 1 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, 0, 16 },
|
Package() { 0x000AFFFF, 1, 0, 17 },
|
Package() { 0x000AFFFF, 2, 0, 18 },
|
Package() { 0x000AFFFF, 3, 0, 19 },
|
// [CHA3]: Uncore 1 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, 0, 16 },
|
Package() { 0x000BFFFF, 1, 0, 17 },
|
Package() { 0x000BFFFF, 2, 0, 18 },
|
Package() { 0x000BFFFF, 3, 0, 19 },
|
// [CHA4]: Uncore 1 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, 0, 16 },
|
Package() { 0x000EFFFF, 1, 0, 17 },
|
Package() { 0x000EFFFF, 2, 0, 18 },
|
Package() { 0x000EFFFF, 3, 0, 19 },
|
// [CHA5]: Uncore 1 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, 0, 16 },
|
Package() { 0x000FFFFF, 1, 0, 17 },
|
Package() { 0x000FFFFF, 2, 0, 18 },
|
Package() { 0x000FFFFF, 3, 0, 19 },
|
// [CHA6]: Uncore 1 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, 0, 16 },
|
Package() { 0x0010FFFF, 1, 0, 17 },
|
Package() { 0x0010FFFF, 2, 0, 18 },
|
Package() { 0x0010FFFF, 3, 0, 19 },
|
// [CHA7]: Uncore 1 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, 0, 16 },
|
Package() { 0x0011FFFF, 1, 0, 17 },
|
Package() { 0x0011FFFF, 2, 0, 18 },
|
Package() { 0x0011FFFF, 3, 0, 19 },
|
// [CMS0]: Uncore 1 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, 0, 16 },
|
Package() { 0x0014FFFF, 1, 0, 17 },
|
Package() { 0x0014FFFF, 2, 0, 18 },
|
Package() { 0x0014FFFF, 3, 0, 19 },
|
// [CMS1]: Uncore 1 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, 0, 16 },
|
Package() { 0x0015FFFF, 1, 0, 17 },
|
Package() { 0x0015FFFF, 2, 0, 18 },
|
Package() { 0x0015FFFF, 3, 0, 19 },
|
// [CMS2]: Uncore 1 CMS0CHA16-23 Device
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [CMS3]: Uncore 1 CMS0CHA24-27 Device
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
// [CDL0]: Uncore 1 CHASADALL Device
|
Package() { 0x001DFFFF, 0, 0, 16 },
|
Package() { 0x001DFFFF, 1, 0, 17 },
|
Package() { 0x001DFFFF, 2, 0, 18 },
|
Package() { 0x001DFFFF, 3, 0, 19 },
|
// [PCU0]: Uncore 1 PCUCR Devices
|
Package() { 0x001EFFFF, 0, 0, 16 },
|
Package() { 0x001EFFFF, 1, 0, 17 },
|
Package() { 0x001EFFFF, 2, 0, 18 },
|
Package() { 0x001EFFFF, 3, 0, 19 },
|
// [VCU0]: Uncore 1 VCUCR Device
|
Package() { 0x001FFFFF, 0, 0, 16 },
|
Package() { 0x001FFFFF, 1, 0, 17 },
|
Package() { 0x001FFFFF, 2, 0, 18 },
|
Package() { 0x001FFFFF, 3, 0, 19 },
|
})
|
|
Name (AH15, Package() {
|
// [BR1A]: PCI Express Port 1A on PC01
|
Package() { 0x0000FFFF, 0, 0, 39 },
|
// [BR1B]: PCI Express Port 1B on PC01
|
Package() { 0x0001FFFF, 0, 0, 39 },
|
// [BR1C]: PCI Express Port 1C on PC01
|
Package() { 0x0002FFFF, 0, 0, 39 },
|
// [BR1D]: PCI Express Port 1D on PC01
|
Package() { 0x0003FFFF, 0, 0, 39 },
|
// [CHA0]: Uncore 1 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, 0, 32 },
|
Package() { 0x0008FFFF, 1, 0, 36 },
|
Package() { 0x0008FFFF, 2, 0, 37 },
|
Package() { 0x0008FFFF, 3, 0, 38 },
|
// [CHA1]: Uncore 1 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, 0, 32 },
|
Package() { 0x0009FFFF, 1, 0, 36 },
|
Package() { 0x0009FFFF, 2, 0, 37 },
|
Package() { 0x0009FFFF, 3, 0, 38 },
|
// [CHA2]: Uncore 1 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, 0, 32 },
|
Package() { 0x000AFFFF, 1, 0, 36 },
|
Package() { 0x000AFFFF, 2, 0, 37 },
|
Package() { 0x000AFFFF, 3, 0, 38 },
|
// [CHA3]: Uncore 1 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, 0, 32 },
|
Package() { 0x000BFFFF, 1, 0, 36 },
|
Package() { 0x000BFFFF, 2, 0, 37 },
|
Package() { 0x000BFFFF, 3, 0, 38 },
|
// [CHA4]: Uncore 1 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, 0, 32 },
|
Package() { 0x000EFFFF, 1, 0, 36 },
|
Package() { 0x000EFFFF, 2, 0, 37 },
|
Package() { 0x000EFFFF, 3, 0, 38 },
|
// [CHA5]: Uncore 1 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, 0, 32 },
|
Package() { 0x000FFFFF, 1, 0, 36 },
|
Package() { 0x000FFFFF, 2, 0, 37 },
|
Package() { 0x000FFFFF, 3, 0, 38 },
|
// [CHA6]: Uncore 1 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, 0, 32 },
|
Package() { 0x0010FFFF, 1, 0, 36 },
|
Package() { 0x0010FFFF, 2, 0, 37 },
|
Package() { 0x0010FFFF, 3, 0, 38 },
|
// [CHA7]: Uncore 1 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, 0, 32 },
|
Package() { 0x0011FFFF, 1, 0, 36 },
|
Package() { 0x0011FFFF, 2, 0, 37 },
|
Package() { 0x0011FFFF, 3, 0, 38 },
|
// [CMS0]: Uncore 1 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, 0, 32 },
|
Package() { 0x0014FFFF, 1, 0, 36 },
|
Package() { 0x0014FFFF, 2, 0, 37 },
|
Package() { 0x0014FFFF, 3, 0, 38 },
|
// [CMS1]: Uncore 1 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, 0, 32 },
|
Package() { 0x0015FFFF, 1, 0, 36 },
|
Package() { 0x0015FFFF, 2, 0, 37 },
|
Package() { 0x0015FFFF, 3, 0, 38 },
|
// [CMS2]: Uncore 1 CMS0CHA16-23 Device
|
Package() { 0x0016FFFF, 0, 0, 32 },
|
Package() { 0x0016FFFF, 1, 0, 36 },
|
Package() { 0x0016FFFF, 2, 0, 37 },
|
Package() { 0x0016FFFF, 3, 0, 38 },
|
// [CMS3]: Uncore 1 CMS0CHA24-27 Device
|
Package() { 0x0017FFFF, 0, 0, 32 },
|
Package() { 0x0017FFFF, 1, 0, 36 },
|
Package() { 0x0017FFFF, 2, 0, 37 },
|
Package() { 0x0017FFFF, 3, 0, 38 },
|
// [CDL0]: Uncore 1 CHASADALL Device
|
Package() { 0x001DFFFF, 0, 0, 32 },
|
Package() { 0x001DFFFF, 1, 0, 36 },
|
Package() { 0x001DFFFF, 2, 0, 37 },
|
Package() { 0x001DFFFF, 3, 0, 38 },
|
// [PCU0]: Uncore 1 PCUCR Devices
|
Package() { 0x001EFFFF, 0, 0, 32 },
|
Package() { 0x001EFFFF, 1, 0, 36 },
|
Package() { 0x001EFFFF, 2, 0, 37 },
|
Package() { 0x001EFFFF, 3, 0, 38 },
|
// [VCU0]: Uncore 1 VCUCR Device
|
Package() { 0x001FFFFF, 0, 0, 32 },
|
Package() { 0x001FFFFF, 1, 0, 36 },
|
Package() { 0x001FFFFF, 2, 0, 37 },
|
Package() { 0x001FFFFF, 3, 0, 38 },
|
})
|
|
Name (PR16, Package() {
|
// [SL01]: PCI Express Slot 1 on 1A on PC01
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR16, Package() {
|
// [SL01]: PCI Express Slot 1 on 1A on PC01
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH16, Package() {
|
// [SL01]: PCI Express Slot 1 on 1A on PC01
|
Package() { 0x0000FFFF, 0, 0, 32 },
|
Package() { 0x0000FFFF, 1, 0, 36 },
|
Package() { 0x0000FFFF, 2, 0, 37 },
|
Package() { 0x0000FFFF, 3, 0, 38 },
|
})
|
|
Name (PR17, Package() {
|
// [SL02]: PCI Express Slot 2 on 1B on PC01
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR17, Package() {
|
// [SL02]: PCI Express Slot 2 on 1B on PC01
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH17, Package() {
|
// [SL02]: PCI Express Slot 2 on 1B on PC01
|
Package() { 0x0000FFFF, 0, 0, 33 },
|
Package() { 0x0000FFFF, 1, 0, 38 },
|
Package() { 0x0000FFFF, 2, 0, 36 },
|
Package() { 0x0000FFFF, 3, 0, 37 },
|
})
|
|
Name (PR18, Package() {
|
// [SL03]: PCI Express Slot 3 on 1C on PC01
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR18, Package() {
|
// [SL03]: PCI Express Slot 3 on 1C on PC01
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH18, Package() {
|
// [SL03]: PCI Express Slot 3 on 1C on PC01
|
Package() { 0x0000FFFF, 0, 0, 34 },
|
Package() { 0x0000FFFF, 1, 0, 37 },
|
Package() { 0x0000FFFF, 2, 0, 38 },
|
Package() { 0x0000FFFF, 3, 0, 36 },
|
})
|
|
Name (PR19, Package() {
|
// [SL04]: PCI Express Slot 4 on 1D on PC01
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR19, Package() {
|
// [SL04]: PCI Express Slot 4 on 1D on PC01
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH19, Package() {
|
// [SL04]: PCI Express Slot 4 on 1D on PC01
|
Package() { 0x0000FFFF, 0, 0, 35 },
|
Package() { 0x0000FFFF, 1, 0, 38 },
|
Package() { 0x0000FFFF, 2, 0, 36 },
|
Package() { 0x0000FFFF, 3, 0, 37 },
|
})
|
|
Name (PR1A, Package() {
|
// [BR2A]: PCI Express Port 2A on PC02
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [BR2B]: PCI Express Port 2B on PC02
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [BR2C]: PCI Express Port 2C on PC02
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [BR2D]: PCI Express Port 2D on PC02
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [M2M0]: Uncore 2 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2M1]: Uncore 2 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCM0]: Uncore 2 MCMAIN Device
|
Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCD0]: Uncore 2 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCM1]: Uncore 2 MCMAIN Device
|
Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCD1]: Uncore 2 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR1A, Package() {
|
// [BR2A]: PCI Express Port 2A on PC02
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [BR2B]: PCI Express Port 2B on PC02
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [BR2C]: PCI Express Port 2C on PC02
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [BR2D]: PCI Express Port 2D on PC02
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [M2M0]: Uncore 2 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
// [M2M1]: Uncore 2 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, 0, 16 },
|
Package() { 0x0009FFFF, 1, 0, 17 },
|
Package() { 0x0009FFFF, 2, 0, 18 },
|
Package() { 0x0009FFFF, 3, 0, 19 },
|
// [MCM0]: Uncore 2 MCMAIN Device
|
Package() { 0x000AFFFF, 0, 0, 16 },
|
Package() { 0x000AFFFF, 1, 0, 17 },
|
Package() { 0x000AFFFF, 2, 0, 18 },
|
Package() { 0x000AFFFF, 3, 0, 19 },
|
// [MCD0]: Uncore 2 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, 0, 16 },
|
Package() { 0x000BFFFF, 1, 0, 17 },
|
Package() { 0x000BFFFF, 2, 0, 18 },
|
Package() { 0x000BFFFF, 3, 0, 19 },
|
// [MCM1]: Uncore 2 MCMAIN Device
|
Package() { 0x000CFFFF, 0, 0, 16 },
|
Package() { 0x000CFFFF, 1, 0, 17 },
|
Package() { 0x000CFFFF, 2, 0, 18 },
|
Package() { 0x000CFFFF, 3, 0, 19 },
|
// [MCD1]: Uncore 2 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, 0, 16 },
|
Package() { 0x000DFFFF, 1, 0, 17 },
|
Package() { 0x000DFFFF, 2, 0, 18 },
|
Package() { 0x000DFFFF, 3, 0, 19 },
|
// [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
})
|
|
Name (AH1A, Package() {
|
// [BR2A]: PCI Express Port 2A on PC02
|
Package() { 0x0000FFFF, 0, 0, 47 },
|
// [BR2B]: PCI Express Port 2B on PC02
|
Package() { 0x0001FFFF, 0, 0, 47 },
|
// [BR2C]: PCI Express Port 2C on PC02
|
Package() { 0x0002FFFF, 0, 0, 47 },
|
// [BR2D]: PCI Express Port 2D on PC02
|
Package() { 0x0003FFFF, 0, 0, 47 },
|
// [M2M0]: Uncore 2 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, 0, 40 },
|
Package() { 0x0008FFFF, 1, 0, 44 },
|
Package() { 0x0008FFFF, 2, 0, 45 },
|
Package() { 0x0008FFFF, 3, 0, 46 },
|
// [M2M1]: Uncore 2 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, 0, 40 },
|
Package() { 0x0009FFFF, 1, 0, 44 },
|
Package() { 0x0009FFFF, 2, 0, 45 },
|
Package() { 0x0009FFFF, 3, 0, 46 },
|
// [MCM0]: Uncore 2 MCMAIN Device
|
Package() { 0x000AFFFF, 0, 0, 40 },
|
Package() { 0x000AFFFF, 1, 0, 44 },
|
Package() { 0x000AFFFF, 2, 0, 45 },
|
Package() { 0x000AFFFF, 3, 0, 46 },
|
// [MCD0]: Uncore 2 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, 0, 40 },
|
Package() { 0x000BFFFF, 1, 0, 44 },
|
Package() { 0x000BFFFF, 2, 0, 45 },
|
Package() { 0x000BFFFF, 3, 0, 46 },
|
// [MCM1]: Uncore 2 MCMAIN Device
|
Package() { 0x000CFFFF, 0, 0, 40 },
|
Package() { 0x000CFFFF, 1, 0, 44 },
|
Package() { 0x000CFFFF, 2, 0, 45 },
|
Package() { 0x000CFFFF, 3, 0, 46 },
|
// [MCD1]: Uncore 2 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, 0, 40 },
|
Package() { 0x000DFFFF, 1, 0, 44 },
|
Package() { 0x000DFFFF, 2, 0, 45 },
|
Package() { 0x000DFFFF, 3, 0, 46 },
|
// [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, 0, 40 },
|
Package() { 0x0016FFFF, 1, 0, 44 },
|
Package() { 0x0016FFFF, 2, 0, 45 },
|
Package() { 0x0016FFFF, 3, 0, 46 },
|
// [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, 0, 40 },
|
Package() { 0x0017FFFF, 1, 0, 44 },
|
Package() { 0x0017FFFF, 2, 0, 45 },
|
Package() { 0x0017FFFF, 3, 0, 46 },
|
})
|
|
Name (PR1B, Package() {
|
// [SL05]: PCI Express Slot 5 on 2A on PC02
|
// [EPCU]: EVA PCIe Uplink
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR1B, Package() {
|
// [SL05]: PCI Express Slot 5 on 2A on PC02
|
// [EPCU]: EVA PCIe Uplink
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH1B, Package() {
|
// [SL05]: PCI Express Slot 5 on 2A on PC02
|
// [EPCU]: EVA PCIe Uplink
|
Package() { 0x0000FFFF, 0, 0, 40 },
|
Package() { 0x0000FFFF, 1, 0, 44 },
|
Package() { 0x0000FFFF, 2, 0, 45 },
|
Package() { 0x0000FFFF, 3, 0, 46 },
|
})
|
|
Name (PR1C, Package() {
|
// [VSP0]: EVA Virtual Switch Port 0
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [VSP1]: EVA Virtual Switch Port 1
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [VSP2]: EVA Virtual Switch Port 2
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [VSP3]: EVA Virtual Switch Port 3
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR1C, Package() {
|
// [VSP0]: EVA Virtual Switch Port 0
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
// [VSP1]: EVA Virtual Switch Port 1
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [VSP2]: EVA Virtual Switch Port 2
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [VSP3]: EVA Virtual Switch Port 3
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
})
|
|
Name (AH1C, Package() {
|
// [VSP0]: EVA Virtual Switch Port 0
|
Package() { 0x0000FFFF, 0, 0, 40 },
|
Package() { 0x0000FFFF, 1, 0, 44 },
|
Package() { 0x0000FFFF, 2, 0, 45 },
|
Package() { 0x0000FFFF, 3, 0, 46 },
|
// [VSP1]: EVA Virtual Switch Port 1
|
Package() { 0x0001FFFF, 0, 0, 40 },
|
// [VSP2]: EVA Virtual Switch Port 2
|
Package() { 0x0002FFFF, 0, 0, 40 },
|
// [VSP3]: EVA Virtual Switch Port 3
|
Package() { 0x0003FFFF, 0, 0, 40 },
|
})
|
|
Name (PR1D, Package() {
|
// [CPM0]: EVA CPM0
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR1D, Package() {
|
// [CPM0]: EVA CPM0
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH1D, Package() {
|
// [CPM0]: EVA CPM0
|
Package() { 0x0000FFFF, 0, 0, 40 },
|
})
|
|
Name (PR1E, Package() {
|
// [CPM1]: EVA CPM1
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR1E, Package() {
|
// [CPM1]: EVA CPM1
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH1E, Package() {
|
// [CPM1]: EVA CPM1
|
Package() { 0x0000FFFF, 0, 0, 41 },
|
})
|
|
Name (PR1F, Package() {
|
// [CPM2]: EVA CPM2
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR1F, Package() {
|
// [CPM2]: EVA CPM2
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH1F, Package() {
|
// [CPM2]: EVA CPM2
|
Package() { 0x0000FFFF, 0, 0, 45 },
|
})
|
|
Name (PR20, Package() {
|
// [FPK0]: EVA Fort Park 0
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [FPK1]: EVA Fort Park 1
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
// [FPK2]: EVA Fort Park 2
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
// [FPK3]: EVA Fort Park 3
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR20, Package() {
|
// [FPK0]: EVA Fort Park 0
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [FPK1]: EVA Fort Park 1
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
// [FPK2]: EVA Fort Park 2
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
// [FPK3]: EVA Fort Park 3
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH20, Package() {
|
// [FPK0]: EVA Fort Park 0
|
Package() { 0x0000FFFF, 0, 0, 46 },
|
// [FPK1]: EVA Fort Park 1
|
Package() { 0x0000FFFF, 1, 0, 46 },
|
// [FPK2]: EVA Fort Park 2
|
Package() { 0x0000FFFF, 2, 0, 46 },
|
// [FPK3]: EVA Fort Park 3
|
Package() { 0x0000FFFF, 3, 0, 46 },
|
})
|
|
Name (PR21, Package() {
|
// [SL06]: PCI Express Slot 6 on 2B on PC02
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR21, Package() {
|
// [SL06]: PCI Express Slot 6 on 2B on PC02
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH21, Package() {
|
// [SL06]: PCI Express Slot 6 on 2B on PC02
|
Package() { 0x0000FFFF, 0, 0, 41 },
|
Package() { 0x0000FFFF, 1, 0, 46 },
|
Package() { 0x0000FFFF, 2, 0, 44 },
|
Package() { 0x0000FFFF, 3, 0, 45 },
|
})
|
|
Name (PR22, Package() {
|
// [SL07]: PCI Express Slot 7 on 2C on PC02
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR22, Package() {
|
// [SL07]: PCI Express Slot 7 on 2C on PC02
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH22, Package() {
|
// [SL07]: PCI Express Slot 7 on 2C on PC02
|
Package() { 0x0000FFFF, 0, 0, 42 },
|
Package() { 0x0000FFFF, 1, 0, 45 },
|
Package() { 0x0000FFFF, 2, 0, 46 },
|
Package() { 0x0000FFFF, 3, 0, 44 },
|
})
|
|
Name (PR23, Package() {
|
// [SL08]: PCI Express Slot 8 on 2D on PC02
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR23, Package() {
|
// [SL08]: PCI Express Slot 8 on 2D on PC02
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH23, Package() {
|
// [SL08]: PCI Express Slot 8 on 2D on PC02
|
Package() { 0x0000FFFF, 0, 0, 43 },
|
Package() { 0x0000FFFF, 1, 0, 46 },
|
Package() { 0x0000FFFF, 2, 0, 44 },
|
Package() { 0x0000FFFF, 3, 0, 45 },
|
})
|
|
Name (PR24, Package() {
|
// [BR3A]: PCI Express Port 3A on PC03
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [BR3B]: PCI Express Port 3B on PC03
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [BR3C]: PCI Express Port 3C on PC03
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [BR3D]: PCI Express Port 3D on PC03
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [KTI0]: KTI0
|
Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [KTI1]: KTI1
|
Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [KTI2]: KTI2
|
Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M3K0]: M3K0
|
Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2U0]: M2U0
|
Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2D0]: M2D0
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M20]: M20
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR24, Package() {
|
// [BR3A]: PCI Express Port 3A on PC03
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [BR3B]: PCI Express Port 3B on PC03
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [BR3C]: PCI Express Port 3C on PC03
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [BR3D]: PCI Express Port 3D on PC03
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [KTI0]: KTI0
|
Package() { 0x000EFFFF, 0, 0, 16 },
|
Package() { 0x000EFFFF, 1, 0, 17 },
|
Package() { 0x000EFFFF, 2, 0, 18 },
|
Package() { 0x000EFFFF, 3, 0, 19 },
|
// [KTI1]: KTI1
|
Package() { 0x000FFFFF, 0, 0, 16 },
|
Package() { 0x000FFFFF, 1, 0, 17 },
|
Package() { 0x000FFFFF, 2, 0, 18 },
|
Package() { 0x000FFFFF, 3, 0, 19 },
|
// [KTI2]: KTI2
|
Package() { 0x0010FFFF, 0, 0, 16 },
|
Package() { 0x0010FFFF, 1, 0, 17 },
|
Package() { 0x0010FFFF, 2, 0, 18 },
|
Package() { 0x0010FFFF, 3, 0, 19 },
|
// [M3K0]: M3K0
|
Package() { 0x0012FFFF, 0, 0, 16 },
|
Package() { 0x0012FFFF, 1, 0, 17 },
|
Package() { 0x0012FFFF, 2, 0, 18 },
|
Package() { 0x0012FFFF, 3, 0, 19 },
|
// [M2U0]: M2U0
|
Package() { 0x0015FFFF, 0, 0, 16 },
|
Package() { 0x0015FFFF, 1, 0, 17 },
|
Package() { 0x0015FFFF, 2, 0, 18 },
|
Package() { 0x0015FFFF, 3, 0, 19 },
|
// [M2D0]: M2D0
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [M20]: M20
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
})
|
|
Name (AH24, Package() {
|
// [BR3A]: PCI Express Port 3A on PC03
|
Package() { 0x0000FFFF, 0, 0, 55 },
|
// [BR3B]: PCI Express Port 3B on PC03
|
Package() { 0x0001FFFF, 0, 0, 55 },
|
// [BR3C]: PCI Express Port 3C on PC03
|
Package() { 0x0002FFFF, 0, 0, 55 },
|
// [BR3D]: PCI Express Port 3D on PC03
|
Package() { 0x0003FFFF, 0, 0, 55 },
|
// [KTI0]: KTI0
|
Package() { 0x000EFFFF, 0, 0, 48 },
|
Package() { 0x000EFFFF, 1, 0, 52 },
|
Package() { 0x000EFFFF, 2, 0, 53 },
|
Package() { 0x000EFFFF, 3, 0, 54 },
|
// [KTI1]: KTI1
|
Package() { 0x000FFFFF, 0, 0, 48 },
|
Package() { 0x000FFFFF, 1, 0, 52 },
|
Package() { 0x000FFFFF, 2, 0, 53 },
|
Package() { 0x000FFFFF, 3, 0, 54 },
|
// [KTI2]: KTI2
|
Package() { 0x0010FFFF, 0, 0, 48 },
|
Package() { 0x0010FFFF, 1, 0, 52 },
|
Package() { 0x0010FFFF, 2, 0, 53 },
|
Package() { 0x0010FFFF, 3, 0, 54 },
|
// [M3K0]: M3K0
|
Package() { 0x0012FFFF, 0, 0, 48 },
|
Package() { 0x0012FFFF, 1, 0, 52 },
|
Package() { 0x0012FFFF, 2, 0, 53 },
|
Package() { 0x0012FFFF, 3, 0, 54 },
|
// [M2U0]: M2U0
|
Package() { 0x0015FFFF, 0, 0, 48 },
|
Package() { 0x0015FFFF, 1, 0, 52 },
|
Package() { 0x0015FFFF, 2, 0, 53 },
|
Package() { 0x0015FFFF, 3, 0, 54 },
|
// [M2D0]: M2D0
|
Package() { 0x0016FFFF, 0, 0, 48 },
|
Package() { 0x0016FFFF, 1, 0, 52 },
|
Package() { 0x0016FFFF, 2, 0, 53 },
|
Package() { 0x0016FFFF, 3, 0, 54 },
|
// [M20]: M20
|
Package() { 0x0017FFFF, 0, 0, 48 },
|
Package() { 0x0017FFFF, 1, 0, 52 },
|
Package() { 0x0017FFFF, 2, 0, 53 },
|
Package() { 0x0017FFFF, 3, 0, 54 },
|
})
|
|
Name (PR25, Package() {
|
// [SL09]: PCI Express Slot 9 on 3A on PC03
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR25, Package() {
|
// [SL09]: PCI Express Slot 9 on 3A on PC03
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH25, Package() {
|
// [SL09]: PCI Express Slot 9 on 3A on PC03
|
Package() { 0x0000FFFF, 0, 0, 48 },
|
Package() { 0x0000FFFF, 1, 0, 52 },
|
Package() { 0x0000FFFF, 2, 0, 53 },
|
Package() { 0x0000FFFF, 3, 0, 54 },
|
})
|
|
Name (PR26, Package() {
|
// [SL0A]: PCI Express Slot 10 on 3B on PC03
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR26, Package() {
|
// [SL0A]: PCI Express Slot 10 on 3B on PC03
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH26, Package() {
|
// [SL0A]: PCI Express Slot 10 on 3B on PC03
|
Package() { 0x0000FFFF, 0, 0, 49 },
|
Package() { 0x0000FFFF, 1, 0, 54 },
|
Package() { 0x0000FFFF, 2, 0, 52 },
|
Package() { 0x0000FFFF, 3, 0, 53 },
|
})
|
|
Name (PR27, Package() {
|
// [SL0B]: PCI Express Slot 11 on 3C on PC03
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR27, Package() {
|
// [SL0B]: PCI Express Slot 11 on 3C on PC03
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH27, Package() {
|
// [SL0B]: PCI Express Slot 11 on 3C on PC03
|
Package() { 0x0000FFFF, 0, 0, 50 },
|
Package() { 0x0000FFFF, 1, 0, 53 },
|
Package() { 0x0000FFFF, 2, 0, 54 },
|
Package() { 0x0000FFFF, 3, 0, 52 },
|
})
|
|
Name (PR28, Package() {
|
// [SL0C]: PCI Express Slot 12 on 3D on PC03
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR28, Package() {
|
// [SL0C]: PCI Express Slot 12 on 3D on PC03
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH28, Package() {
|
// [SL0C]: PCI Express Slot 12 on 3D on PC03
|
Package() { 0x0000FFFF, 0, 0, 51 },
|
Package() { 0x0000FFFF, 1, 0, 54 },
|
Package() { 0x0000FFFF, 2, 0, 52 },
|
Package() { 0x0000FFFF, 3, 0, 53 },
|
})
|
|
Name (PR29, Package() {
|
// [MCP0]: PCI Express Port 4 on PC04
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR29, Package() {
|
// [MCP0]: PCI Express Port 4 on PC04
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH29, Package() {
|
// [MCP0]: PCI Express Port 4 on PC04
|
Package() { 0x0000FFFF, 0, 0, 63 },
|
})
|
|
Name (PR2A, Package() {
|
// [SL0D]: PCI Express Slot 13 on 4 on PC04
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR2A, Package() {
|
// [SL0D]: PCI Express Slot 13 on 4 on PC04
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH2A, Package() {
|
// [SL0D]: PCI Express Slot 13 on 4 on PC04
|
Package() { 0x0000FFFF, 0, 0, 56 },
|
Package() { 0x0000FFFF, 1, 0, 60 },
|
Package() { 0x0000FFFF, 2, 0, 61 },
|
Package() { 0x0000FFFF, 3, 0, 62 },
|
})
|
|
Name (PR2B, Package() {
|
// [MCP1]: PCI Express Port 5 on PC05
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR2B, Package() {
|
// [MCP1]: PCI Express Port 5 on PC05
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH2B, Package() {
|
// [MCP1]: PCI Express Port 5 on PC05
|
Package() { 0x0000FFFF, 0, 0, 71 },
|
})
|
|
Name (PR2C, Package() {
|
// [SL0E]: PCI Express Slot 14 on 5 on PC05
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR2C, Package() {
|
// [SL0E]: PCI Express Slot 14 on 5 on PC05
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH2C, Package() {
|
// [SL0E]: PCI Express Slot 14 on 5 on PC05
|
Package() { 0x0000FFFF, 0, 0, 64 },
|
Package() { 0x0000FFFF, 1, 0, 68 },
|
Package() { 0x0000FFFF, 2, 0, 69 },
|
Package() { 0x0000FFFF, 3, 0, 70 },
|
})
|
|
Name (PR2D, Package() {
|
// [QRP0]: PCI Express Port 0 on PC06
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [CB1B]: CB3DMA on PC06
|
// [CB1F]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
// [CB1C]: CB3DMA on PC06
|
// [CB1G]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
// [CB1D]: CB3DMA on PC06
|
// [CB1H]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CB1E]: CB3DMA on PC06
|
// [CB1A]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [IIM1]: IIOMISC on PC01
|
Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UBX1]: Uncore 4 UBOX Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR2D, Package() {
|
// [QRP0]: PCI Express Port 0 on PC06
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [CB1B]: CB3DMA on PC06
|
// [CB1F]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 1, 0, 17 },
|
// [CB1C]: CB3DMA on PC06
|
// [CB1G]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 2, 0, 18 },
|
// [CB1D]: CB3DMA on PC06
|
// [CB1H]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 3, 0, 19 },
|
// [CB1E]: CB3DMA on PC06
|
// [CB1A]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 0, 0, 16 },
|
// [IIM1]: IIOMISC on PC01
|
Package() { 0x0005FFFF, 0, 0, 16 },
|
Package() { 0x0005FFFF, 1, 0, 17 },
|
Package() { 0x0005FFFF, 2, 0, 18 },
|
Package() { 0x0005FFFF, 3, 0, 19 },
|
// [UBX1]: Uncore 4 UBOX Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
})
|
|
Name (AH2D, Package() {
|
// [QRP0]: PCI Express Port 0 on PC06
|
Package() { 0x0000FFFF, 0, 0, 79 },
|
// [CB1B]: CB3DMA on PC06
|
// [CB1F]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 1, 0, 75 },
|
// [CB1C]: CB3DMA on PC06
|
// [CB1G]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 2, 0, 74 },
|
// [CB1D]: CB3DMA on PC06
|
// [CB1H]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 3, 0, 75 },
|
// [CB1E]: CB3DMA on PC06
|
// [CB1A]: CB3DMA on PC06
|
Package() { 0x0004FFFF, 0, 0, 74 },
|
// [IIM1]: IIOMISC on PC01
|
Package() { 0x0005FFFF, 0, 0, 16 },
|
Package() { 0x0005FFFF, 1, 0, 17 },
|
Package() { 0x0005FFFF, 2, 0, 18 },
|
Package() { 0x0005FFFF, 3, 0, 19 },
|
// [UBX1]: Uncore 4 UBOX Device
|
Package() { 0x0008FFFF, 0, 0, 72 },
|
Package() { 0x0008FFFF, 1, 0, 76 },
|
Package() { 0x0008FFFF, 2, 0, 77 },
|
Package() { 0x0008FFFF, 3, 0, 78 },
|
})
|
|
Name (PR2E, Package() {
|
// [SL0F]: PCI Express Slot 15 on P0 on PC06
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR2E, Package() {
|
// [SL0F]: PCI Express Slot 15 on P0 on PC06
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH2E, Package() {
|
// [SL0F]: PCI Express Slot 15 on P0 on PC06
|
Package() { 0x0000FFFF, 0, 0, 72 },
|
Package() { 0x0000FFFF, 1, 0, 76 },
|
Package() { 0x0000FFFF, 2, 0, 77 },
|
Package() { 0x0000FFFF, 3, 0, 78 },
|
})
|
|
Name (PR2F, Package() {
|
// [QR1A]: PCI Express Port 1A on PC07
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [QR1B]: PCI Express Port 1B on PC07
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [QR1C]: PCI Express Port 1C on PC07
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [QR1D]: PCI Express Port 1D on PC07
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [CHB0]: Uncore 5 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHB1]: Uncore 5 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHB2]: Uncore 5 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHB3]: Uncore 5 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHB4]: Uncore 5 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHB5]: Uncore 5 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHB6]: Uncore 5 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHB7]: Uncore 5 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS4]: Uncore 5 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS5]: Uncore 5 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS6]: Uncore 5 CMS0CHA16-23 Device
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS7]: Uncore 5 CMS0CHA24-27 Device
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CDL1]: Uncore 5 CHASADALL Device
|
Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [PCU1]: Uncore 5 PCUCR Devices
|
Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [VCU1]: Uncore 5 VCUCR Device
|
Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR2F, Package() {
|
// [QR1A]: PCI Express Port 1A on PC07
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [QR1B]: PCI Express Port 1B on PC07
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [QR1C]: PCI Express Port 1C on PC07
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [QR1D]: PCI Express Port 1D on PC07
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [CHB0]: Uncore 5 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
// [CHB1]: Uncore 5 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, 0, 16 },
|
Package() { 0x0009FFFF, 1, 0, 17 },
|
Package() { 0x0009FFFF, 2, 0, 18 },
|
Package() { 0x0009FFFF, 3, 0, 19 },
|
// [CHB2]: Uncore 5 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, 0, 16 },
|
Package() { 0x000AFFFF, 1, 0, 17 },
|
Package() { 0x000AFFFF, 2, 0, 18 },
|
Package() { 0x000AFFFF, 3, 0, 19 },
|
// [CHB3]: Uncore 5 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, 0, 16 },
|
Package() { 0x000BFFFF, 1, 0, 17 },
|
Package() { 0x000BFFFF, 2, 0, 18 },
|
Package() { 0x000BFFFF, 3, 0, 19 },
|
// [CHB4]: Uncore 5 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, 0, 16 },
|
Package() { 0x000EFFFF, 1, 0, 17 },
|
Package() { 0x000EFFFF, 2, 0, 18 },
|
Package() { 0x000EFFFF, 3, 0, 19 },
|
// [CHB5]: Uncore 5 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, 0, 16 },
|
Package() { 0x000FFFFF, 1, 0, 17 },
|
Package() { 0x000FFFFF, 2, 0, 18 },
|
Package() { 0x000FFFFF, 3, 0, 19 },
|
// [CHB6]: Uncore 5 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, 0, 16 },
|
Package() { 0x0010FFFF, 1, 0, 17 },
|
Package() { 0x0010FFFF, 2, 0, 18 },
|
Package() { 0x0010FFFF, 3, 0, 19 },
|
// [CHB7]: Uncore 5 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, 0, 16 },
|
Package() { 0x0011FFFF, 1, 0, 17 },
|
Package() { 0x0011FFFF, 2, 0, 18 },
|
Package() { 0x0011FFFF, 3, 0, 19 },
|
// [CMS4]: Uncore 5 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, 0, 16 },
|
Package() { 0x0014FFFF, 1, 0, 17 },
|
Package() { 0x0014FFFF, 2, 0, 18 },
|
Package() { 0x0014FFFF, 3, 0, 19 },
|
// [CMS5]: Uncore 5 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, 0, 16 },
|
Package() { 0x0015FFFF, 1, 0, 17 },
|
Package() { 0x0015FFFF, 2, 0, 18 },
|
Package() { 0x0015FFFF, 3, 0, 19 },
|
// [CMS6]: Uncore 5 CMS0CHA16-23 Device
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [CMS7]: Uncore 5 CMS0CHA24-27 Device
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
// [CDL1]: Uncore 5 CHASADALL Device
|
Package() { 0x001DFFFF, 0, 0, 16 },
|
Package() { 0x001DFFFF, 1, 0, 17 },
|
Package() { 0x001DFFFF, 2, 0, 18 },
|
Package() { 0x001DFFFF, 3, 0, 19 },
|
// [PCU1]: Uncore 5 PCUCR Devices
|
Package() { 0x001EFFFF, 0, 0, 16 },
|
Package() { 0x001EFFFF, 1, 0, 17 },
|
Package() { 0x001EFFFF, 2, 0, 18 },
|
Package() { 0x001EFFFF, 3, 0, 19 },
|
// [VCU1]: Uncore 5 VCUCR Device
|
Package() { 0x001FFFFF, 0, 0, 16 },
|
Package() { 0x001FFFFF, 1, 0, 17 },
|
Package() { 0x001FFFFF, 2, 0, 18 },
|
Package() { 0x001FFFFF, 3, 0, 19 },
|
})
|
|
Name (AH2F, Package() {
|
// [QR1A]: PCI Express Port 1A on PC07
|
Package() { 0x0000FFFF, 0, 0, 87 },
|
// [QR1B]: PCI Express Port 1B on PC07
|
Package() { 0x0001FFFF, 0, 0, 87 },
|
// [QR1C]: PCI Express Port 1C on PC07
|
Package() { 0x0002FFFF, 0, 0, 87 },
|
// [QR1D]: PCI Express Port 1D on PC07
|
Package() { 0x0003FFFF, 0, 0, 87 },
|
// [CHB0]: Uncore 5 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, 0, 80 },
|
Package() { 0x0008FFFF, 1, 0, 84 },
|
Package() { 0x0008FFFF, 2, 0, 85 },
|
Package() { 0x0008FFFF, 3, 0, 86 },
|
// [CHB1]: Uncore 5 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, 0, 80 },
|
Package() { 0x0009FFFF, 1, 0, 84 },
|
Package() { 0x0009FFFF, 2, 0, 85 },
|
Package() { 0x0009FFFF, 3, 0, 86 },
|
// [CHB2]: Uncore 5 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, 0, 80 },
|
Package() { 0x000AFFFF, 1, 0, 84 },
|
Package() { 0x000AFFFF, 2, 0, 85 },
|
Package() { 0x000AFFFF, 3, 0, 86 },
|
// [CHB3]: Uncore 5 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, 0, 80 },
|
Package() { 0x000BFFFF, 1, 0, 84 },
|
Package() { 0x000BFFFF, 2, 0, 85 },
|
Package() { 0x000BFFFF, 3, 0, 86 },
|
// [CHB4]: Uncore 5 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, 0, 80 },
|
Package() { 0x000EFFFF, 1, 0, 84 },
|
Package() { 0x000EFFFF, 2, 0, 85 },
|
Package() { 0x000EFFFF, 3, 0, 86 },
|
// [CHB5]: Uncore 5 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, 0, 80 },
|
Package() { 0x000FFFFF, 1, 0, 84 },
|
Package() { 0x000FFFFF, 2, 0, 85 },
|
Package() { 0x000FFFFF, 3, 0, 86 },
|
// [CHB6]: Uncore 5 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, 0, 80 },
|
Package() { 0x0010FFFF, 1, 0, 84 },
|
Package() { 0x0010FFFF, 2, 0, 85 },
|
Package() { 0x0010FFFF, 3, 0, 86 },
|
// [CHB7]: Uncore 5 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, 0, 80 },
|
Package() { 0x0011FFFF, 1, 0, 84 },
|
Package() { 0x0011FFFF, 2, 0, 85 },
|
Package() { 0x0011FFFF, 3, 0, 86 },
|
// [CMS4]: Uncore 5 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, 0, 80 },
|
Package() { 0x0014FFFF, 1, 0, 84 },
|
Package() { 0x0014FFFF, 2, 0, 85 },
|
Package() { 0x0014FFFF, 3, 0, 86 },
|
// [CMS5]: Uncore 5 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, 0, 80 },
|
Package() { 0x0015FFFF, 1, 0, 84 },
|
Package() { 0x0015FFFF, 2, 0, 85 },
|
Package() { 0x0015FFFF, 3, 0, 86 },
|
// [CMS6]: Uncore 5 CMS0CHA16-23 Device
|
Package() { 0x0016FFFF, 0, 0, 80 },
|
Package() { 0x0016FFFF, 1, 0, 84 },
|
Package() { 0x0016FFFF, 2, 0, 85 },
|
Package() { 0x0016FFFF, 3, 0, 86 },
|
// [CMS7]: Uncore 5 CMS0CHA24-27 Device
|
Package() { 0x0017FFFF, 0, 0, 80 },
|
Package() { 0x0017FFFF, 1, 0, 84 },
|
Package() { 0x0017FFFF, 2, 0, 85 },
|
Package() { 0x0017FFFF, 3, 0, 86 },
|
// [CDL1]: Uncore 5 CHASADALL Device
|
Package() { 0x001DFFFF, 0, 0, 80 },
|
Package() { 0x001DFFFF, 1, 0, 84 },
|
Package() { 0x001DFFFF, 2, 0, 85 },
|
Package() { 0x001DFFFF, 3, 0, 86 },
|
// [PCU1]: Uncore 5 PCUCR Devices
|
Package() { 0x001EFFFF, 0, 0, 80 },
|
Package() { 0x001EFFFF, 1, 0, 84 },
|
Package() { 0x001EFFFF, 2, 0, 85 },
|
Package() { 0x001EFFFF, 3, 0, 86 },
|
// [VCU1]: Uncore 5 VCUCR Device
|
Package() { 0x001FFFFF, 0, 0, 80 },
|
Package() { 0x001FFFFF, 1, 0, 84 },
|
Package() { 0x001FFFFF, 2, 0, 85 },
|
Package() { 0x001FFFFF, 3, 0, 86 },
|
})
|
|
Name (PR30, Package() {
|
// [SL10]: PCI Express Slot 16 on 1A on PC07
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR30, Package() {
|
// [SL10]: PCI Express Slot 16 on 1A on PC07
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH30, Package() {
|
// [SL10]: PCI Express Slot 16 on 1A on PC07
|
Package() { 0x0000FFFF, 0, 0, 80 },
|
Package() { 0x0000FFFF, 1, 0, 84 },
|
Package() { 0x0000FFFF, 2, 0, 85 },
|
Package() { 0x0000FFFF, 3, 0, 86 },
|
})
|
|
Name (PR31, Package() {
|
// [SL11]: PCI Express Slot 17 on 1B on PC07
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR31, Package() {
|
// [SL11]: PCI Express Slot 17 on 1B on PC07
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH31, Package() {
|
// [SL11]: PCI Express Slot 17 on 1B on PC07
|
Package() { 0x0000FFFF, 0, 0, 81 },
|
Package() { 0x0000FFFF, 1, 0, 86 },
|
Package() { 0x0000FFFF, 2, 0, 84 },
|
Package() { 0x0000FFFF, 3, 0, 85 },
|
})
|
|
Name (PR32, Package() {
|
// [SL12]: PCI Express Slot 18 on 1C on PC07
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR32, Package() {
|
// [SL12]: PCI Express Slot 18 on 1C on PC07
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH32, Package() {
|
// [SL12]: PCI Express Slot 18 on 1C on PC07
|
Package() { 0x0000FFFF, 0, 0, 82 },
|
Package() { 0x0000FFFF, 1, 0, 85 },
|
Package() { 0x0000FFFF, 2, 0, 86 },
|
Package() { 0x0000FFFF, 3, 0, 84 },
|
})
|
|
Name (PR33, Package() {
|
// [SL13]: PCI Express Slot 19 on 1D on PC07
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR33, Package() {
|
// [SL13]: PCI Express Slot 19 on 1D on PC07
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH33, Package() {
|
// [SL13]: PCI Express Slot 19 on 1D on PC07
|
Package() { 0x0000FFFF, 0, 0, 83 },
|
Package() { 0x0000FFFF, 1, 0, 86 },
|
Package() { 0x0000FFFF, 2, 0, 84 },
|
Package() { 0x0000FFFF, 3, 0, 85 },
|
})
|
|
Name (PR34, Package() {
|
// [QR2A]: PCI Express Port 2A on PC08
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [QR2B]: PCI Express Port 2B on PC08
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [QR2C]: PCI Express Port 2C on PC08
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [QR2D]: PCI Express Port 2D on PC08
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [M2M2]: Uncore 6 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2M3]: Uncore 6 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCM2]: Uncore 6 MCMAIN Device
|
Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCD2]: Uncore 6 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCM3]: Uncore 6 MCMAIN Device
|
Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCD3]: Uncore 6 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR34, Package() {
|
// [QR2A]: PCI Express Port 2A on PC08
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [QR2B]: PCI Express Port 2B on PC08
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [QR2C]: PCI Express Port 2C on PC08
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [QR2D]: PCI Express Port 2D on PC08
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [M2M2]: Uncore 6 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
// [M2M3]: Uncore 6 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, 0, 16 },
|
Package() { 0x0009FFFF, 1, 0, 17 },
|
Package() { 0x0009FFFF, 2, 0, 18 },
|
Package() { 0x0009FFFF, 3, 0, 19 },
|
// [MCM2]: Uncore 6 MCMAIN Device
|
Package() { 0x000AFFFF, 0, 0, 16 },
|
Package() { 0x000AFFFF, 1, 0, 17 },
|
Package() { 0x000AFFFF, 2, 0, 18 },
|
Package() { 0x000AFFFF, 3, 0, 19 },
|
// [MCD2]: Uncore 6 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, 0, 16 },
|
Package() { 0x000BFFFF, 1, 0, 17 },
|
Package() { 0x000BFFFF, 2, 0, 18 },
|
Package() { 0x000BFFFF, 3, 0, 19 },
|
// [MCM3]: Uncore 6 MCMAIN Device
|
Package() { 0x000CFFFF, 0, 0, 16 },
|
Package() { 0x000CFFFF, 1, 0, 17 },
|
Package() { 0x000CFFFF, 2, 0, 18 },
|
Package() { 0x000CFFFF, 3, 0, 19 },
|
// [MCD3]: Uncore 6 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, 0, 16 },
|
Package() { 0x000DFFFF, 1, 0, 17 },
|
Package() { 0x000DFFFF, 2, 0, 18 },
|
Package() { 0x000DFFFF, 3, 0, 19 },
|
// [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
})
|
|
Name (AH34, Package() {
|
// [QR2A]: PCI Express Port 2A on PC08
|
Package() { 0x0000FFFF, 0, 0, 95 },
|
// [QR2B]: PCI Express Port 2B on PC08
|
Package() { 0x0001FFFF, 0, 0, 95 },
|
// [QR2C]: PCI Express Port 2C on PC08
|
Package() { 0x0002FFFF, 0, 0, 95 },
|
// [QR2D]: PCI Express Port 2D on PC08
|
Package() { 0x0003FFFF, 0, 0, 95 },
|
// [M2M2]: Uncore 6 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, 0, 88 },
|
Package() { 0x0008FFFF, 1, 0, 92 },
|
Package() { 0x0008FFFF, 2, 0, 93 },
|
Package() { 0x0008FFFF, 3, 0, 94 },
|
// [M2M3]: Uncore 6 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, 0, 88 },
|
Package() { 0x0009FFFF, 1, 0, 92 },
|
Package() { 0x0009FFFF, 2, 0, 93 },
|
Package() { 0x0009FFFF, 3, 0, 94 },
|
// [MCM2]: Uncore 6 MCMAIN Device
|
Package() { 0x000AFFFF, 0, 0, 88 },
|
Package() { 0x000AFFFF, 1, 0, 92 },
|
Package() { 0x000AFFFF, 2, 0, 93 },
|
Package() { 0x000AFFFF, 3, 0, 94 },
|
// [MCD2]: Uncore 6 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, 0, 88 },
|
Package() { 0x000BFFFF, 1, 0, 92 },
|
Package() { 0x000BFFFF, 2, 0, 93 },
|
Package() { 0x000BFFFF, 3, 0, 94 },
|
// [MCM3]: Uncore 6 MCMAIN Device
|
Package() { 0x000CFFFF, 0, 0, 88 },
|
Package() { 0x000CFFFF, 1, 0, 92 },
|
Package() { 0x000CFFFF, 2, 0, 93 },
|
Package() { 0x000CFFFF, 3, 0, 94 },
|
// [MCD3]: Uncore 6 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, 0, 88 },
|
Package() { 0x000DFFFF, 1, 0, 92 },
|
Package() { 0x000DFFFF, 2, 0, 93 },
|
Package() { 0x000DFFFF, 3, 0, 94 },
|
// [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, 0, 88 },
|
Package() { 0x0016FFFF, 1, 0, 92 },
|
Package() { 0x0016FFFF, 2, 0, 93 },
|
Package() { 0x0016FFFF, 3, 0, 94 },
|
// [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, 0, 88 },
|
Package() { 0x0017FFFF, 1, 0, 92 },
|
Package() { 0x0017FFFF, 2, 0, 93 },
|
Package() { 0x0017FFFF, 3, 0, 94 },
|
})
|
|
Name (PR35, Package() {
|
// [SL14]: PCI Express Slot 20 on 2A on PC08
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR35, Package() {
|
// [SL14]: PCI Express Slot 20 on 2A on PC08
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH35, Package() {
|
// [SL14]: PCI Express Slot 20 on 2A on PC08
|
Package() { 0x0000FFFF, 0, 0, 88 },
|
Package() { 0x0000FFFF, 1, 0, 92 },
|
Package() { 0x0000FFFF, 2, 0, 93 },
|
Package() { 0x0000FFFF, 3, 0, 94 },
|
})
|
|
Name (PR36, Package() {
|
// [SL15]: PCI Express Slot 21 on 2B on PC08
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR36, Package() {
|
// [SL15]: PCI Express Slot 21 on 2B on PC08
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH36, Package() {
|
// [SL15]: PCI Express Slot 21 on 2B on PC08
|
Package() { 0x0000FFFF, 0, 0, 89 },
|
Package() { 0x0000FFFF, 1, 0, 94 },
|
Package() { 0x0000FFFF, 2, 0, 92 },
|
Package() { 0x0000FFFF, 3, 0, 93 },
|
})
|
|
Name (PR37, Package() {
|
// [SL16]: PCI Express Slot 22 on 2C on PC08
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR37, Package() {
|
// [SL16]: PCI Express Slot 22 on 2C on PC08
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH37, Package() {
|
// [SL16]: PCI Express Slot 22 on 2C on PC08
|
Package() { 0x0000FFFF, 0, 0, 90 },
|
Package() { 0x0000FFFF, 1, 0, 93 },
|
Package() { 0x0000FFFF, 2, 0, 94 },
|
Package() { 0x0000FFFF, 3, 0, 92 },
|
})
|
|
Name (PR38, Package() {
|
// [SL17]: PCI Express Slot 23 on 2D on PC08
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR38, Package() {
|
// [SL17]: PCI Express Slot 23 on 2D on PC08
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH38, Package() {
|
// [SL17]: PCI Express Slot 23 on 2D on PC08
|
Package() { 0x0000FFFF, 0, 0, 91 },
|
Package() { 0x0000FFFF, 1, 0, 94 },
|
Package() { 0x0000FFFF, 2, 0, 92 },
|
Package() { 0x0000FFFF, 3, 0, 93 },
|
})
|
|
Name (PR39, Package() {
|
// [QR3A]: PCI Express Port 3A on PC09
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [QR3B]: PCI Express Port 3B on PC09
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [QR3C]: PCI Express Port 3C on PC09
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [QR3D]: PCI Express Port 3D on PC09
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [KTI3]: Uncore 7 KTI3
|
Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [KTI4]: Uncore 7 KTI4
|
Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [KTI5]: Uncore 7 KTI5
|
Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M3K1]: Uncore 7 M3K1
|
Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2U1]: Uncore 7 M2U1
|
Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2D1]: Uncore 7 M2D1
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M21]: Uncore 7 M21
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR39, Package() {
|
// [QR3A]: PCI Express Port 3A on PC09
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [QR3B]: PCI Express Port 3B on PC09
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [QR3C]: PCI Express Port 3C on PC09
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [QR3D]: PCI Express Port 3D on PC09
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [KTI3]: Uncore 7 KTI3
|
Package() { 0x000EFFFF, 0, 0, 16 },
|
Package() { 0x000EFFFF, 1, 0, 17 },
|
Package() { 0x000EFFFF, 2, 0, 18 },
|
Package() { 0x000EFFFF, 3, 0, 19 },
|
// [KTI4]: Uncore 7 KTI4
|
Package() { 0x000FFFFF, 0, 0, 16 },
|
Package() { 0x000FFFFF, 1, 0, 17 },
|
Package() { 0x000FFFFF, 2, 0, 18 },
|
Package() { 0x000FFFFF, 3, 0, 19 },
|
// [KTI5]: Uncore 7 KTI5
|
Package() { 0x0010FFFF, 0, 0, 16 },
|
Package() { 0x0010FFFF, 1, 0, 17 },
|
Package() { 0x0010FFFF, 2, 0, 18 },
|
Package() { 0x0010FFFF, 3, 0, 19 },
|
// [M3K1]: Uncore 7 M3K1
|
Package() { 0x0012FFFF, 0, 0, 16 },
|
Package() { 0x0012FFFF, 1, 0, 17 },
|
Package() { 0x0012FFFF, 2, 0, 18 },
|
Package() { 0x0012FFFF, 3, 0, 19 },
|
// [M2U1]: Uncore 7 M2U1
|
Package() { 0x0015FFFF, 0, 0, 16 },
|
Package() { 0x0015FFFF, 1, 0, 17 },
|
Package() { 0x0015FFFF, 2, 0, 18 },
|
Package() { 0x0015FFFF, 3, 0, 19 },
|
// [M2D1]: Uncore 7 M2D1
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [M21]: Uncore 7 M21
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
})
|
|
Name (AH39, Package() {
|
// [QR3A]: PCI Express Port 3A on PC09
|
Package() { 0x0000FFFF, 0, 0, 103 },
|
// [QR3B]: PCI Express Port 3B on PC09
|
Package() { 0x0001FFFF, 0, 0, 103 },
|
// [QR3C]: PCI Express Port 3C on PC09
|
Package() { 0x0002FFFF, 0, 0, 103 },
|
// [QR3D]: PCI Express Port 3D on PC09
|
Package() { 0x0003FFFF, 0, 0, 103 },
|
// [KTI3]: Uncore 7 KTI3
|
Package() { 0x000EFFFF, 0, 0, 96 },
|
Package() { 0x000EFFFF, 1, 0, 100 },
|
Package() { 0x000EFFFF, 2, 0, 101 },
|
Package() { 0x000EFFFF, 3, 0, 102 },
|
// [KTI4]: Uncore 7 KTI4
|
Package() { 0x000FFFFF, 0, 0, 96 },
|
Package() { 0x000FFFFF, 1, 0, 100 },
|
Package() { 0x000FFFFF, 2, 0, 101 },
|
Package() { 0x000FFFFF, 3, 0, 102 },
|
// [KTI5]: Uncore 7 KTI5
|
Package() { 0x0010FFFF, 0, 0, 96 },
|
Package() { 0x0010FFFF, 1, 0, 100 },
|
Package() { 0x0010FFFF, 2, 0, 101 },
|
Package() { 0x0010FFFF, 3, 0, 102 },
|
// [M3K1]: Uncore 7 M3K1
|
Package() { 0x0012FFFF, 0, 0, 96 },
|
Package() { 0x0012FFFF, 1, 0, 100 },
|
Package() { 0x0012FFFF, 2, 0, 101 },
|
Package() { 0x0012FFFF, 3, 0, 102 },
|
// [M2U1]: Uncore 7 M2U1
|
Package() { 0x0015FFFF, 0, 0, 96 },
|
Package() { 0x0015FFFF, 1, 0, 100 },
|
Package() { 0x0015FFFF, 2, 0, 101 },
|
Package() { 0x0015FFFF, 3, 0, 102 },
|
// [M2D1]: Uncore 7 M2D1
|
Package() { 0x0016FFFF, 0, 0, 96 },
|
Package() { 0x0016FFFF, 1, 0, 100 },
|
Package() { 0x0016FFFF, 2, 0, 101 },
|
Package() { 0x0016FFFF, 3, 0, 102 },
|
// [M21]: Uncore 7 M21
|
Package() { 0x0017FFFF, 0, 0, 96 },
|
Package() { 0x0017FFFF, 1, 0, 100 },
|
Package() { 0x0017FFFF, 2, 0, 101 },
|
Package() { 0x0017FFFF, 3, 0, 102 },
|
})
|
|
Name (PR3A, Package() {
|
// [SL18]: PCI Express Slot 24 on 3A on PC09
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR3A, Package() {
|
// [SL18]: PCI Express Slot 24 on 3A on PC09
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH3A, Package() {
|
// [SL18]: PCI Express Slot 24 on 3A on PC09
|
Package() { 0x0000FFFF, 0, 0, 96 },
|
Package() { 0x0000FFFF, 1, 0, 100 },
|
Package() { 0x0000FFFF, 2, 0, 101 },
|
Package() { 0x0000FFFF, 3, 0, 102 },
|
})
|
|
Name (PR3B, Package() {
|
// [SL19]: PCI Express Slot 25 on 3B on PC09
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR3B, Package() {
|
// [SL19]: PCI Express Slot 25 on 3B on PC09
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH3B, Package() {
|
// [SL19]: PCI Express Slot 25 on 3B on PC09
|
Package() { 0x0000FFFF, 0, 0, 97 },
|
Package() { 0x0000FFFF, 1, 0, 102 },
|
Package() { 0x0000FFFF, 2, 0, 100 },
|
Package() { 0x0000FFFF, 3, 0, 101 },
|
})
|
|
Name (PR3C, Package() {
|
// [SL1A]: PCI Express Slot 26 on 3C on PC09
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR3C, Package() {
|
// [SL1A]: PCI Express Slot 26 on 3C on PC09
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH3C, Package() {
|
// [SL1A]: PCI Express Slot 26 on 3C on PC09
|
Package() { 0x0000FFFF, 0, 0, 98 },
|
Package() { 0x0000FFFF, 1, 0, 101 },
|
Package() { 0x0000FFFF, 2, 0, 102 },
|
Package() { 0x0000FFFF, 3, 0, 100 },
|
})
|
|
Name (PR3D, Package() {
|
// [SL1B]: PCI Express Slot 27 on 3D on PC09
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR3D, Package() {
|
// [SL1B]: PCI Express Slot 27 on 3D on PC09
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH3D, Package() {
|
// [SL1B]: PCI Express Slot 27 on 3D on PC09
|
Package() { 0x0000FFFF, 0, 0, 99 },
|
Package() { 0x0000FFFF, 1, 0, 102 },
|
Package() { 0x0000FFFF, 2, 0, 100 },
|
Package() { 0x0000FFFF, 3, 0, 101 },
|
})
|
|
Name (PR3E, Package() {
|
// [MCP2]: PCI Express Port 13 on PC10
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR3E, Package() {
|
// [MCP2]: PCI Express Port 13 on PC10
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH3E, Package() {
|
// [MCP2]: PCI Express Port 13 on PC10
|
Package() { 0x0000FFFF, 0, 0, 111 },
|
})
|
|
Name (PR3F, Package() {
|
// [SL1C]: PCI Express Slot 28 on 4 on PC10
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR3F, Package() {
|
// [SL1C]: PCI Express Slot 28 on 4 on PC10
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH3F, Package() {
|
// [SL1C]: PCI Express Slot 28 on 4 on PC10
|
Package() { 0x0000FFFF, 0, 0, 104 },
|
Package() { 0x0000FFFF, 1, 0, 108 },
|
Package() { 0x0000FFFF, 2, 0, 109 },
|
Package() { 0x0000FFFF, 3, 0, 110 },
|
})
|
|
Name (PR40, Package() {
|
// [MCP3]: PCI Express Port 14 on PC11
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR40, Package() {
|
// [MCP3]: PCI Express Port 14 on PC11
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH40, Package() {
|
// [MCP3]: PCI Express Port 14 on PC11
|
Package() { 0x0000FFFF, 0, 0, 119 },
|
})
|
|
Name (PR41, Package() {
|
// [SL1D]: PCI Express Slot 29 on 5 on PC11
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR41, Package() {
|
// [SL1D]: PCI Express Slot 29 on 5 on PC11
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH41, Package() {
|
// [SL1D]: PCI Express Slot 29 on 5 on PC11
|
Package() { 0x0000FFFF, 0, 0, 112 },
|
Package() { 0x0000FFFF, 1, 0, 116 },
|
Package() { 0x0000FFFF, 2, 0, 117 },
|
Package() { 0x0000FFFF, 3, 0, 118 },
|
})
|
|
Name (PR42, Package() {
|
// [RRP0]: PCI Express Port 0 on PC12
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [CB2B]: CB3DMA on PC12
|
// [CB2F]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
// [CB2C]: CB3DMA on PC12
|
// [CB2G]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
// [CB2D]: CB3DMA on PC12
|
// [CB2H]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CB2E]: CB3DMA on PC12
|
// [CB2A]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [IIM2]: IIOMISC on PC02
|
Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UBX2]: Uncore 8 UBOX Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR42, Package() {
|
// [RRP0]: PCI Express Port 0 on PC12
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [CB2B]: CB3DMA on PC12
|
// [CB2F]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 1, 0, 17 },
|
// [CB2C]: CB3DMA on PC12
|
// [CB2G]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 2, 0, 18 },
|
// [CB2D]: CB3DMA on PC12
|
// [CB2H]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 3, 0, 19 },
|
// [CB2E]: CB3DMA on PC12
|
// [CB2A]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 0, 0, 16 },
|
// [IIM2]: IIOMISC on PC02
|
Package() { 0x0005FFFF, 0, 0, 16 },
|
Package() { 0x0005FFFF, 1, 0, 17 },
|
Package() { 0x0005FFFF, 2, 0, 18 },
|
Package() { 0x0005FFFF, 3, 0, 19 },
|
// [UBX2]: Uncore 8 UBOX Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
})
|
|
Name (AH42, Package() {
|
// [RRP0]: PCI Express Port 0 on PC12
|
Package() { 0x0000FFFF, 0, 0, 127 },
|
// [CB2B]: CB3DMA on PC12
|
// [CB2F]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 1, 0, 123 },
|
// [CB2C]: CB3DMA on PC12
|
// [CB2G]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 2, 0, 122 },
|
// [CB2D]: CB3DMA on PC12
|
// [CB2H]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 3, 0, 123 },
|
// [CB2E]: CB3DMA on PC12
|
// [CB2A]: CB3DMA on PC12
|
Package() { 0x0004FFFF, 0, 0, 122 },
|
// [IIM2]: IIOMISC on PC02
|
Package() { 0x0005FFFF, 0, 0, 16 },
|
Package() { 0x0005FFFF, 1, 0, 17 },
|
Package() { 0x0005FFFF, 2, 0, 18 },
|
Package() { 0x0005FFFF, 3, 0, 19 },
|
// [UBX2]: Uncore 8 UBOX Device
|
Package() { 0x0008FFFF, 0, 0, 120 },
|
Package() { 0x0008FFFF, 1, 0, 124 },
|
Package() { 0x0008FFFF, 2, 0, 125 },
|
Package() { 0x0008FFFF, 3, 0, 126 },
|
})
|
|
Name (PR43, Package() {
|
// [SL1E]: PCI Express Slot 30 on P0 on PC12
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR43, Package() {
|
// [SL1E]: PCI Express Slot 30 on P0 on PC12
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH43, Package() {
|
// [SL1E]: PCI Express Slot 30 on P0 on PC12
|
Package() { 0x0000FFFF, 0, 0, 120 },
|
Package() { 0x0000FFFF, 1, 0, 124 },
|
Package() { 0x0000FFFF, 2, 0, 125 },
|
Package() { 0x0000FFFF, 3, 0, 126 },
|
})
|
|
Name (PR44, Package() {
|
// [RR1A]: PCI Express Port 1A on PC13
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [RR1B]: PCI Express Port 1B on PC13
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [RR1C]: PCI Express Port 1C on PC13
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [RR1D]: PCI Express Port 1D on PC13
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [CHC0]: Uncore 9 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHC1]: Uncore 9 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHC2]: Uncore 9 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHC3]: Uncore 9 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHC4]: Uncore 9 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHC5]: Uncore 9 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHC6]: Uncore 9 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHC7]: Uncore 9 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS8]: Uncore 9 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CMS9]: Uncore 9 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CDL2]: Uncore 9 CHASADALL Device
|
Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [PCU2]: Uncore 9 PCUCR Devices
|
Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [VCU2]: Uncore 9 VCUCR Device
|
Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR44, Package() {
|
// [RR1A]: PCI Express Port 1A on PC13
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [RR1B]: PCI Express Port 1B on PC13
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [RR1C]: PCI Express Port 1C on PC13
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [RR1D]: PCI Express Port 1D on PC13
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [CHC0]: Uncore 9 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
// [CHC1]: Uncore 9 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, 0, 16 },
|
Package() { 0x0009FFFF, 1, 0, 17 },
|
Package() { 0x0009FFFF, 2, 0, 18 },
|
Package() { 0x0009FFFF, 3, 0, 19 },
|
// [CHC2]: Uncore 9 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, 0, 16 },
|
Package() { 0x000AFFFF, 1, 0, 17 },
|
Package() { 0x000AFFFF, 2, 0, 18 },
|
Package() { 0x000AFFFF, 3, 0, 19 },
|
// [CHC3]: Uncore 9 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, 0, 16 },
|
Package() { 0x000BFFFF, 1, 0, 17 },
|
Package() { 0x000BFFFF, 2, 0, 18 },
|
Package() { 0x000BFFFF, 3, 0, 19 },
|
// [CHC4]: Uncore 9 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, 0, 16 },
|
Package() { 0x000EFFFF, 1, 0, 17 },
|
Package() { 0x000EFFFF, 2, 0, 18 },
|
Package() { 0x000EFFFF, 3, 0, 19 },
|
// [CHC5]: Uncore 9 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, 0, 16 },
|
Package() { 0x000FFFFF, 1, 0, 17 },
|
Package() { 0x000FFFFF, 2, 0, 18 },
|
Package() { 0x000FFFFF, 3, 0, 19 },
|
// [CHC6]: Uncore 9 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, 0, 16 },
|
Package() { 0x0010FFFF, 1, 0, 17 },
|
Package() { 0x0010FFFF, 2, 0, 18 },
|
Package() { 0x0010FFFF, 3, 0, 19 },
|
// [CHC7]: Uncore 9 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, 0, 16 },
|
Package() { 0x0011FFFF, 1, 0, 17 },
|
Package() { 0x0011FFFF, 2, 0, 18 },
|
Package() { 0x0011FFFF, 3, 0, 19 },
|
// [CMS8]: Uncore 9 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, 0, 16 },
|
Package() { 0x0014FFFF, 1, 0, 17 },
|
Package() { 0x0014FFFF, 2, 0, 18 },
|
Package() { 0x0014FFFF, 3, 0, 19 },
|
// [CMS9]: Uncore 9 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, 0, 16 },
|
Package() { 0x0015FFFF, 1, 0, 17 },
|
Package() { 0x0015FFFF, 2, 0, 18 },
|
Package() { 0x0015FFFF, 3, 0, 19 },
|
// [CDL2]: Uncore 9 CHASADALL Device
|
Package() { 0x001DFFFF, 0, 0, 16 },
|
Package() { 0x001DFFFF, 1, 0, 17 },
|
Package() { 0x001DFFFF, 2, 0, 18 },
|
Package() { 0x001DFFFF, 3, 0, 19 },
|
// [PCU2]: Uncore 9 PCUCR Devices
|
Package() { 0x001EFFFF, 0, 0, 16 },
|
Package() { 0x001EFFFF, 1, 0, 17 },
|
Package() { 0x001EFFFF, 2, 0, 18 },
|
Package() { 0x001EFFFF, 3, 0, 19 },
|
// [VCU2]: Uncore 9 VCUCR Device
|
Package() { 0x001FFFFF, 0, 0, 16 },
|
Package() { 0x001FFFFF, 1, 0, 17 },
|
Package() { 0x001FFFFF, 2, 0, 18 },
|
Package() { 0x001FFFFF, 3, 0, 19 },
|
})
|
|
Name (AH44, Package() {
|
// [RR1A]: PCI Express Port 1A on PC13
|
Package() { 0x0000FFFF, 0, 0, 135 },
|
// [RR1B]: PCI Express Port 1B on PC13
|
Package() { 0x0001FFFF, 0, 0, 135 },
|
// [RR1C]: PCI Express Port 1C on PC13
|
Package() { 0x0002FFFF, 0, 0, 135 },
|
// [RR1D]: PCI Express Port 1D on PC13
|
Package() { 0x0003FFFF, 0, 0, 135 },
|
// [CHC0]: Uncore 9 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, 0, 128 },
|
Package() { 0x0008FFFF, 1, 0, 132 },
|
Package() { 0x0008FFFF, 2, 0, 133 },
|
Package() { 0x0008FFFF, 3, 0, 134 },
|
// [CHC1]: Uncore 9 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, 0, 128 },
|
Package() { 0x0009FFFF, 1, 0, 132 },
|
Package() { 0x0009FFFF, 2, 0, 133 },
|
Package() { 0x0009FFFF, 3, 0, 134 },
|
// [CHC2]: Uncore 9 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, 0, 128 },
|
Package() { 0x000AFFFF, 1, 0, 132 },
|
Package() { 0x000AFFFF, 2, 0, 133 },
|
Package() { 0x000AFFFF, 3, 0, 134 },
|
// [CHC3]: Uncore 9 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, 0, 128 },
|
Package() { 0x000BFFFF, 1, 0, 132 },
|
Package() { 0x000BFFFF, 2, 0, 133 },
|
Package() { 0x000BFFFF, 3, 0, 134 },
|
// [CHC4]: Uncore 9 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, 0, 128 },
|
Package() { 0x000EFFFF, 1, 0, 132 },
|
Package() { 0x000EFFFF, 2, 0, 133 },
|
Package() { 0x000EFFFF, 3, 0, 134 },
|
// [CHC5]: Uncore 9 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, 0, 128 },
|
Package() { 0x000FFFFF, 1, 0, 132 },
|
Package() { 0x000FFFFF, 2, 0, 133 },
|
Package() { 0x000FFFFF, 3, 0, 134 },
|
// [CHC6]: Uncore 9 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, 0, 128 },
|
Package() { 0x0010FFFF, 1, 0, 132 },
|
Package() { 0x0010FFFF, 2, 0, 133 },
|
Package() { 0x0010FFFF, 3, 0, 134 },
|
// [CHC7]: Uncore 9 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, 0, 128 },
|
Package() { 0x0011FFFF, 1, 0, 132 },
|
Package() { 0x0011FFFF, 2, 0, 133 },
|
Package() { 0x0011FFFF, 3, 0, 134 },
|
// [CMS8]: Uncore 9 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, 0, 128 },
|
Package() { 0x0014FFFF, 1, 0, 132 },
|
Package() { 0x0014FFFF, 2, 0, 133 },
|
Package() { 0x0014FFFF, 3, 0, 134 },
|
// [CMS9]: Uncore 9 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, 0, 128 },
|
Package() { 0x0015FFFF, 1, 0, 132 },
|
Package() { 0x0015FFFF, 2, 0, 133 },
|
Package() { 0x0015FFFF, 3, 0, 134 },
|
// [CDL2]: Uncore 9 CHASADALL Device
|
Package() { 0x001DFFFF, 0, 0, 128 },
|
Package() { 0x001DFFFF, 1, 0, 132 },
|
Package() { 0x001DFFFF, 2, 0, 133 },
|
Package() { 0x001DFFFF, 3, 0, 134 },
|
// [PCU2]: Uncore 9 PCUCR Devices
|
Package() { 0x001EFFFF, 0, 0, 128 },
|
Package() { 0x001EFFFF, 1, 0, 132 },
|
Package() { 0x001EFFFF, 2, 0, 133 },
|
Package() { 0x001EFFFF, 3, 0, 134 },
|
// [VCU2]: Uncore 9 VCUCR Device
|
Package() { 0x001FFFFF, 0, 0, 128 },
|
Package() { 0x001FFFFF, 1, 0, 132 },
|
Package() { 0x001FFFFF, 2, 0, 133 },
|
Package() { 0x001FFFFF, 3, 0, 134 },
|
})
|
|
Name (PR45, Package() {
|
// [SL1F]: PCI Express Slot 31 on 1A on PC13
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR45, Package() {
|
// [SL1F]: PCI Express Slot 31 on 1A on PC13
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH45, Package() {
|
// [SL1F]: PCI Express Slot 31 on 1A on PC13
|
Package() { 0x0000FFFF, 0, 0, 128 },
|
Package() { 0x0000FFFF, 1, 0, 132 },
|
Package() { 0x0000FFFF, 2, 0, 133 },
|
Package() { 0x0000FFFF, 3, 0, 134 },
|
})
|
|
Name (PR46, Package() {
|
// [SL20]: PCI Express Slot 32 on 1B on PC13
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR46, Package() {
|
// [SL20]: PCI Express Slot 32 on 1B on PC13
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH46, Package() {
|
// [SL20]: PCI Express Slot 32 on 1B on PC13
|
Package() { 0x0000FFFF, 0, 0, 129 },
|
Package() { 0x0000FFFF, 1, 0, 134 },
|
Package() { 0x0000FFFF, 2, 0, 132 },
|
Package() { 0x0000FFFF, 3, 0, 133 },
|
})
|
|
Name (PR47, Package() {
|
// [SL21]: PCI Express Slot 33 on 1C on PC13
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR47, Package() {
|
// [SL21]: PCI Express Slot 33 on 1C on PC13
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH47, Package() {
|
// [SL21]: PCI Express Slot 33 on 1C on PC13
|
Package() { 0x0000FFFF, 0, 0, 130 },
|
Package() { 0x0000FFFF, 1, 0, 133 },
|
Package() { 0x0000FFFF, 2, 0, 134 },
|
Package() { 0x0000FFFF, 3, 0, 132 },
|
})
|
|
Name (PR48, Package() {
|
// [SL22]: PCI Express Slot 34 on 1D on PC13
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR48, Package() {
|
// [SL22]: PCI Express Slot 34 on 1D on PC13
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH48, Package() {
|
// [SL22]: PCI Express Slot 34 on 1D on PC13
|
Package() { 0x0000FFFF, 0, 0, 131 },
|
Package() { 0x0000FFFF, 1, 0, 134 },
|
Package() { 0x0000FFFF, 2, 0, 132 },
|
Package() { 0x0000FFFF, 3, 0, 133 },
|
})
|
|
Name (PR49, Package() {
|
// [RR2A]: PCI Express Port 2A on PC14
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [RR2B]: PCI Express Port 2B on PC14
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [RR2C]: PCI Express Port 2C on PC14
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [RR2D]: PCI Express Port 2D on PC14
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [M2M4]: Uncore 10 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2M5]: Uncore 10 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCM4]: Uncore 10 MCMAIN Device
|
Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCD4]: Uncore 10 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCM5]: Uncore 10 MCMAIN Device
|
Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCD5]: Uncore 10 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR49, Package() {
|
// [RR2A]: PCI Express Port 2A on PC14
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [RR2B]: PCI Express Port 2B on PC14
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [RR2C]: PCI Express Port 2C on PC14
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [RR2D]: PCI Express Port 2D on PC14
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [M2M4]: Uncore 10 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
// [M2M5]: Uncore 10 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, 0, 16 },
|
Package() { 0x0009FFFF, 1, 0, 17 },
|
Package() { 0x0009FFFF, 2, 0, 18 },
|
Package() { 0x0009FFFF, 3, 0, 19 },
|
// [MCM4]: Uncore 10 MCMAIN Device
|
Package() { 0x000AFFFF, 0, 0, 16 },
|
Package() { 0x000AFFFF, 1, 0, 17 },
|
Package() { 0x000AFFFF, 2, 0, 18 },
|
Package() { 0x000AFFFF, 3, 0, 19 },
|
// [MCD4]: Uncore 10 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, 0, 16 },
|
Package() { 0x000BFFFF, 1, 0, 17 },
|
Package() { 0x000BFFFF, 2, 0, 18 },
|
Package() { 0x000BFFFF, 3, 0, 19 },
|
// [MCM5]: Uncore 10 MCMAIN Device
|
Package() { 0x000CFFFF, 0, 0, 16 },
|
Package() { 0x000CFFFF, 1, 0, 17 },
|
Package() { 0x000CFFFF, 2, 0, 18 },
|
Package() { 0x000CFFFF, 3, 0, 19 },
|
// [MCD5]: Uncore 10 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, 0, 16 },
|
Package() { 0x000DFFFF, 1, 0, 17 },
|
Package() { 0x000DFFFF, 2, 0, 18 },
|
Package() { 0x000DFFFF, 3, 0, 19 },
|
// [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
})
|
|
Name (AH49, Package() {
|
// [RR2A]: PCI Express Port 2A on PC14
|
Package() { 0x0000FFFF, 0, 0, 143 },
|
// [RR2B]: PCI Express Port 2B on PC14
|
Package() { 0x0001FFFF, 0, 0, 143 },
|
// [RR2C]: PCI Express Port 2C on PC14
|
Package() { 0x0002FFFF, 0, 0, 143 },
|
// [RR2D]: PCI Express Port 2D on PC14
|
Package() { 0x0003FFFF, 0, 0, 143 },
|
// [M2M4]: Uncore 10 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, 0, 136 },
|
Package() { 0x0008FFFF, 1, 0, 140 },
|
Package() { 0x0008FFFF, 2, 0, 141 },
|
Package() { 0x0008FFFF, 3, 0, 142 },
|
// [M2M5]: Uncore 10 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, 0, 136 },
|
Package() { 0x0009FFFF, 1, 0, 140 },
|
Package() { 0x0009FFFF, 2, 0, 141 },
|
Package() { 0x0009FFFF, 3, 0, 142 },
|
// [MCM4]: Uncore 10 MCMAIN Device
|
Package() { 0x000AFFFF, 0, 0, 136 },
|
Package() { 0x000AFFFF, 1, 0, 140 },
|
Package() { 0x000AFFFF, 2, 0, 141 },
|
Package() { 0x000AFFFF, 3, 0, 142 },
|
// [MCD4]: Uncore 10 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, 0, 136 },
|
Package() { 0x000BFFFF, 1, 0, 140 },
|
Package() { 0x000BFFFF, 2, 0, 141 },
|
Package() { 0x000BFFFF, 3, 0, 142 },
|
// [MCM5]: Uncore 10 MCMAIN Device
|
Package() { 0x000CFFFF, 0, 0, 136 },
|
Package() { 0x000CFFFF, 1, 0, 140 },
|
Package() { 0x000CFFFF, 2, 0, 141 },
|
Package() { 0x000CFFFF, 3, 0, 142 },
|
// [MCD5]: Uncore 10 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, 0, 136 },
|
Package() { 0x000DFFFF, 1, 0, 140 },
|
Package() { 0x000DFFFF, 2, 0, 141 },
|
Package() { 0x000DFFFF, 3, 0, 142 },
|
// [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, 0, 136 },
|
Package() { 0x0016FFFF, 1, 0, 140 },
|
Package() { 0x0016FFFF, 2, 0, 141 },
|
Package() { 0x0016FFFF, 3, 0, 142 },
|
// [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, 0, 136 },
|
Package() { 0x0017FFFF, 1, 0, 140 },
|
Package() { 0x0017FFFF, 2, 0, 141 },
|
Package() { 0x0017FFFF, 3, 0, 142 },
|
})
|
|
Name (PR4A, Package() {
|
// [SL23]: PCI Express Slot 35 on 2A on PC14
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR4A, Package() {
|
// [SL23]: PCI Express Slot 35 on 2A on PC14
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH4A, Package() {
|
// [SL23]: PCI Express Slot 35 on 2A on PC14
|
Package() { 0x0000FFFF, 0, 0, 136 },
|
Package() { 0x0000FFFF, 1, 0, 140 },
|
Package() { 0x0000FFFF, 2, 0, 141 },
|
Package() { 0x0000FFFF, 3, 0, 142 },
|
})
|
|
Name (PR4B, Package() {
|
// [SL24]: PCI Express Slot 36 on 2B on PC14
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR4B, Package() {
|
// [SL24]: PCI Express Slot 36 on 2B on PC14
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH4B, Package() {
|
// [SL24]: PCI Express Slot 36 on 2B on PC14
|
Package() { 0x0000FFFF, 0, 0, 137 },
|
Package() { 0x0000FFFF, 1, 0, 142 },
|
Package() { 0x0000FFFF, 2, 0, 140 },
|
Package() { 0x0000FFFF, 3, 0, 141 },
|
})
|
|
Name (PR4C, Package() {
|
// [SL25]: PCI Express Slot 37 on 2C on PC14
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR4C, Package() {
|
// [SL25]: PCI Express Slot 37 on 2C on PC14
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH4C, Package() {
|
// [SL25]: PCI Express Slot 37 on 2C on PC14
|
Package() { 0x0000FFFF, 0, 0, 138 },
|
Package() { 0x0000FFFF, 1, 0, 141 },
|
Package() { 0x0000FFFF, 2, 0, 142 },
|
Package() { 0x0000FFFF, 3, 0, 140 },
|
})
|
|
Name (PR4D, Package() {
|
// [SL26]: PCI Express Slot 38 on 2D on PC14
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR4D, Package() {
|
// [SL26]: PCI Express Slot 38 on 2D on PC14
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH4D, Package() {
|
// [SL26]: PCI Express Slot 38 on 2D on PC14
|
Package() { 0x0000FFFF, 0, 0, 139 },
|
Package() { 0x0000FFFF, 1, 0, 142 },
|
Package() { 0x0000FFFF, 2, 0, 140 },
|
Package() { 0x0000FFFF, 3, 0, 141 },
|
})
|
|
Name (PR4E, Package() {
|
// [RR3A]: PCI Express Port 3A on PC15
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [RR3B]: PCI Express Port 3B on PC15
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [RR3C]: PCI Express Port 3C on PC15
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [RR3D]: PCI Express Port 3D on PC15
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [KTI6]: Uncore 11 KTI6
|
Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [KTI7]: Uncore 11 KTI7
|
Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [KTI8]: Uncore 11 KTI8
|
Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M3K2]: Uncore 11 M3K2
|
Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2U2]: Uncore 11 M2U2
|
Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2D2]: Uncore 11 M2D2
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M22]: Uncore 11 M22
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR4E, Package() {
|
// [RR3A]: PCI Express Port 3A on PC15
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [RR3B]: PCI Express Port 3B on PC15
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [RR3C]: PCI Express Port 3C on PC15
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [RR3D]: PCI Express Port 3D on PC15
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [KTI6]: Uncore 11 KTI6
|
Package() { 0x000EFFFF, 0, 0, 16 },
|
Package() { 0x000EFFFF, 1, 0, 17 },
|
Package() { 0x000EFFFF, 2, 0, 18 },
|
Package() { 0x000EFFFF, 3, 0, 19 },
|
// [KTI7]: Uncore 11 KTI7
|
Package() { 0x000FFFFF, 0, 0, 16 },
|
Package() { 0x000FFFFF, 1, 0, 17 },
|
Package() { 0x000FFFFF, 2, 0, 18 },
|
Package() { 0x000FFFFF, 3, 0, 19 },
|
// [KTI8]: Uncore 11 KTI8
|
Package() { 0x0010FFFF, 0, 0, 16 },
|
Package() { 0x0010FFFF, 1, 0, 17 },
|
Package() { 0x0010FFFF, 2, 0, 18 },
|
Package() { 0x0010FFFF, 3, 0, 19 },
|
// [M3K2]: Uncore 11 M3K2
|
Package() { 0x0012FFFF, 0, 0, 16 },
|
Package() { 0x0012FFFF, 1, 0, 17 },
|
Package() { 0x0012FFFF, 2, 0, 18 },
|
Package() { 0x0012FFFF, 3, 0, 19 },
|
// [M2U2]: Uncore 11 M2U2
|
Package() { 0x0015FFFF, 0, 0, 16 },
|
Package() { 0x0015FFFF, 1, 0, 17 },
|
Package() { 0x0015FFFF, 2, 0, 18 },
|
Package() { 0x0015FFFF, 3, 0, 19 },
|
// [M2D2]: Uncore 11 M2D2
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [M22]: Uncore 11 M22
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
})
|
|
Name (AH4E, Package() {
|
// [RR3A]: PCI Express Port 3A on PC15
|
Package() { 0x0000FFFF, 0, 0, 151 },
|
// [RR3B]: PCI Express Port 3B on PC15
|
Package() { 0x0001FFFF, 0, 0, 151 },
|
// [RR3C]: PCI Express Port 3C on PC15
|
Package() { 0x0002FFFF, 0, 0, 151 },
|
// [RR3D]: PCI Express Port 3D on PC15
|
Package() { 0x0003FFFF, 0, 0, 151 },
|
// [KTI6]: Uncore 11 KTI6
|
Package() { 0x000EFFFF, 0, 0, 144 },
|
Package() { 0x000EFFFF, 1, 0, 148 },
|
Package() { 0x000EFFFF, 2, 0, 149 },
|
Package() { 0x000EFFFF, 3, 0, 150 },
|
// [KTI7]: Uncore 11 KTI7
|
Package() { 0x000FFFFF, 0, 0, 144 },
|
Package() { 0x000FFFFF, 1, 0, 148 },
|
Package() { 0x000FFFFF, 2, 0, 149 },
|
Package() { 0x000FFFFF, 3, 0, 150 },
|
// [KTI8]: Uncore 11 KTI8
|
Package() { 0x0010FFFF, 0, 0, 144 },
|
Package() { 0x0010FFFF, 1, 0, 148 },
|
Package() { 0x0010FFFF, 2, 0, 149 },
|
Package() { 0x0010FFFF, 3, 0, 150 },
|
// [M3K2]: Uncore 11 M3K2
|
Package() { 0x0012FFFF, 0, 0, 144 },
|
Package() { 0x0012FFFF, 1, 0, 148 },
|
Package() { 0x0012FFFF, 2, 0, 149 },
|
Package() { 0x0012FFFF, 3, 0, 150 },
|
// [M2U2]: Uncore 11 M2U2
|
Package() { 0x0015FFFF, 0, 0, 144 },
|
Package() { 0x0015FFFF, 1, 0, 148 },
|
Package() { 0x0015FFFF, 2, 0, 149 },
|
Package() { 0x0015FFFF, 3, 0, 150 },
|
// [M2D2]: Uncore 11 M2D2
|
Package() { 0x0016FFFF, 0, 0, 144 },
|
Package() { 0x0016FFFF, 1, 0, 148 },
|
Package() { 0x0016FFFF, 2, 0, 149 },
|
Package() { 0x0016FFFF, 3, 0, 150 },
|
// [M22]: Uncore 11 M22
|
Package() { 0x0017FFFF, 0, 0, 144 },
|
Package() { 0x0017FFFF, 1, 0, 148 },
|
Package() { 0x0017FFFF, 2, 0, 149 },
|
Package() { 0x0017FFFF, 3, 0, 150 },
|
})
|
|
Name (PR4F, Package() {
|
// [SL27]: PCI Express Slot 39 on 3A on PC15
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR4F, Package() {
|
// [SL27]: PCI Express Slot 39 on 3A on PC15
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH4F, Package() {
|
// [SL27]: PCI Express Slot 39 on 3A on PC15
|
Package() { 0x0000FFFF, 0, 0, 144 },
|
Package() { 0x0000FFFF, 1, 0, 148 },
|
Package() { 0x0000FFFF, 2, 0, 149 },
|
Package() { 0x0000FFFF, 3, 0, 150 },
|
})
|
|
Name (PR50, Package() {
|
// [SL28]: PCI Express Slot 40 on 3B on PC15
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR50, Package() {
|
// [SL28]: PCI Express Slot 40 on 3B on PC15
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH50, Package() {
|
// [SL28]: PCI Express Slot 40 on 3B on PC15
|
Package() { 0x0000FFFF, 0, 0, 145 },
|
Package() { 0x0000FFFF, 1, 0, 150 },
|
Package() { 0x0000FFFF, 2, 0, 148 },
|
Package() { 0x0000FFFF, 3, 0, 149 },
|
})
|
|
Name (PR51, Package() {
|
// [SL29]: PCI Express Slot 41 on 3C on PC15
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR51, Package() {
|
// [SL29]: PCI Express Slot 41 on 3C on PC15
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH51, Package() {
|
// [SL29]: PCI Express Slot 41 on 3C on PC15
|
Package() { 0x0000FFFF, 0, 0, 146 },
|
Package() { 0x0000FFFF, 1, 0, 149 },
|
Package() { 0x0000FFFF, 2, 0, 150 },
|
Package() { 0x0000FFFF, 3, 0, 148 },
|
})
|
|
Name (PR52, Package() {
|
// [SL2A]: PCI Express Slot 42 on 3D on PC15
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR52, Package() {
|
// [SL2A]: PCI Express Slot 42 on 3D on PC15
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH52, Package() {
|
// [SL2A]: PCI Express Slot 42 on 3D on PC15
|
Package() { 0x0000FFFF, 0, 0, 147 },
|
Package() { 0x0000FFFF, 1, 0, 150 },
|
Package() { 0x0000FFFF, 2, 0, 148 },
|
Package() { 0x0000FFFF, 3, 0, 149 },
|
})
|
|
Name (PR53, Package() {
|
// [MCP4]: PCI Express Port 4 on PC16
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR53, Package() {
|
// [MCP4]: PCI Express Port 4 on PC16
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH53, Package() {
|
// [MCP4]: PCI Express Port 4 on PC16
|
Package() { 0x0000FFFF, 0, 0, 159 },
|
})
|
|
Name (PR54, Package() {
|
// [SL2B]: PCI Express Slot 43 on 4 on PC16
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR54, Package() {
|
// [SL2B]: PCI Express Slot 43 on 4 on PC16
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH54, Package() {
|
// [SL2B]: PCI Express Slot 43 on 4 on PC16
|
Package() { 0x0000FFFF, 0, 0, 152 },
|
Package() { 0x0000FFFF, 1, 0, 156 },
|
Package() { 0x0000FFFF, 2, 0, 157 },
|
Package() { 0x0000FFFF, 3, 0, 158 },
|
})
|
|
Name (PR55, Package() {
|
// [MCP5]: PCI Express Port 5 on PC17
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR55, Package() {
|
// [MCP5]: PCI Express Port 5 on PC17
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH55, Package() {
|
// [MCP5]: PCI Express Port 5 on PC17
|
Package() { 0x0000FFFF, 0, 0, 167 },
|
})
|
|
Name (PR56, Package() {
|
// [SL2C]: PCI Express Slot 44 on 4 on PC17
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR56, Package() {
|
// [SL2C]: PCI Express Slot 44 on 4 on PC17
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH56, Package() {
|
// [SL2C]: PCI Express Slot 44 on 4 on PC17
|
Package() { 0x0000FFFF, 0, 0, 160 },
|
Package() { 0x0000FFFF, 1, 0, 164 },
|
Package() { 0x0000FFFF, 2, 0, 165 },
|
Package() { 0x0000FFFF, 3, 0, 166 },
|
})
|
|
Name (PR57, Package() {
|
// [SRP0]: PCI Express Port 0 on PC18
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [CB3B]: CB3DMA on PC18
|
// [CB3F]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
// [CB3C]: CB3DMA on PC18
|
// [CB3G]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
// [CB3D]: CB3DMA on PC18
|
// [CB3H]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CB3E]: CB3DMA on PC18
|
// [CB3A]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [IIM3]: IIOMISC on PC03
|
Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UBX3]: Uncore 12 UBOX Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR57, Package() {
|
// [SRP0]: PCI Express Port 0 on PC18
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [CB3B]: CB3DMA on PC18
|
// [CB3F]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 1, 0, 17 },
|
// [CB3C]: CB3DMA on PC18
|
// [CB3G]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 2, 0, 18 },
|
// [CB3D]: CB3DMA on PC18
|
// [CB3H]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 3, 0, 19 },
|
// [CB3E]: CB3DMA on PC18
|
// [CB3A]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 0, 0, 16 },
|
// [IIM3]: IIOMISC on PC03
|
Package() { 0x0005FFFF, 0, 0, 16 },
|
Package() { 0x0005FFFF, 1, 0, 17 },
|
Package() { 0x0005FFFF, 2, 0, 18 },
|
Package() { 0x0005FFFF, 3, 0, 19 },
|
// [UBX3]: Uncore 12 UBOX Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
})
|
|
Name (AH57, Package() {
|
// [SRP0]: PCI Express Port 0 on PC18
|
Package() { 0x0000FFFF, 0, 0, 175 },
|
// [CB3B]: CB3DMA on PC18
|
// [CB3F]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 1, 0, 171 },
|
// [CB3C]: CB3DMA on PC18
|
// [CB3G]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 2, 0, 170 },
|
// [CB3D]: CB3DMA on PC18
|
// [CB3H]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 3, 0, 171 },
|
// [CB3E]: CB3DMA on PC18
|
// [CB3A]: CB3DMA on PC18
|
Package() { 0x0004FFFF, 0, 0, 170 },
|
// [IIM3]: IIOMISC on PC03
|
Package() { 0x0005FFFF, 0, 0, 16 },
|
Package() { 0x0005FFFF, 1, 0, 17 },
|
Package() { 0x0005FFFF, 2, 0, 18 },
|
Package() { 0x0005FFFF, 3, 0, 19 },
|
// [UBX3]: Uncore 12 UBOX Device
|
Package() { 0x0008FFFF, 0, 0, 168 },
|
Package() { 0x0008FFFF, 1, 0, 172 },
|
Package() { 0x0008FFFF, 2, 0, 173 },
|
Package() { 0x0008FFFF, 3, 0, 174 },
|
})
|
|
Name (PR58, Package() {
|
// [SL2D]: PCI Express Slot 45 on P0 on PC18
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR58, Package() {
|
// [SL2D]: PCI Express Slot 45 on P0 on PC18
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH58, Package() {
|
// [SL2D]: PCI Express Slot 45 on P0 on PC18
|
Package() { 0x0000FFFF, 0, 0, 168 },
|
Package() { 0x0000FFFF, 1, 0, 172 },
|
Package() { 0x0000FFFF, 2, 0, 173 },
|
Package() { 0x0000FFFF, 3, 0, 174 },
|
})
|
|
Name (PR59, Package() {
|
// [SR1A]: PCI Express Port 1A on PC19
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [SR1B]: PCI Express Port 1B on PC19
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [SR1C]: PCI Express Port 1C on PC19
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [SR1D]: PCI Express Port 1D on PC19
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [CHD0]: Uncore 13 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHD1]: Uncore 13 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHD2]: Uncore 13 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHD3]: Uncore 13 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHD4]: Uncore 13 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHD5]: Uncore 13 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHD6]: Uncore 13 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CHD7]: Uncore 13 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CM12]: Uncore 13 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CM13]: Uncore 13 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CM14]: Uncore 13 CMS0CHA16-23 Device
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CM15]: Uncore 13 CMS0CHA24-27 Device
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [CDL3]: Uncore 13 CHASADALL Device
|
Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [PCU3]: Uncore 13 PCUCR Devices
|
Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [VCU3]: Uncore 13 VCUCR Device
|
Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR59, Package() {
|
// [SR1A]: PCI Express Port 1A on PC19
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [SR1B]: PCI Express Port 1B on PC19
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [SR1C]: PCI Express Port 1C on PC19
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [SR1D]: PCI Express Port 1D on PC19
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [CHD0]: Uncore 13 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
// [CHD1]: Uncore 13 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, 0, 16 },
|
Package() { 0x0009FFFF, 1, 0, 17 },
|
Package() { 0x0009FFFF, 2, 0, 18 },
|
Package() { 0x0009FFFF, 3, 0, 19 },
|
// [CHD2]: Uncore 13 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, 0, 16 },
|
Package() { 0x000AFFFF, 1, 0, 17 },
|
Package() { 0x000AFFFF, 2, 0, 18 },
|
Package() { 0x000AFFFF, 3, 0, 19 },
|
// [CHD3]: Uncore 13 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, 0, 16 },
|
Package() { 0x000BFFFF, 1, 0, 17 },
|
Package() { 0x000BFFFF, 2, 0, 18 },
|
Package() { 0x000BFFFF, 3, 0, 19 },
|
// [CHD4]: Uncore 13 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, 0, 16 },
|
Package() { 0x000EFFFF, 1, 0, 17 },
|
Package() { 0x000EFFFF, 2, 0, 18 },
|
Package() { 0x000EFFFF, 3, 0, 19 },
|
// [CHD5]: Uncore 13 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, 0, 16 },
|
Package() { 0x000FFFFF, 1, 0, 17 },
|
Package() { 0x000FFFFF, 2, 0, 18 },
|
Package() { 0x000FFFFF, 3, 0, 19 },
|
// [CHD6]: Uncore 13 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, 0, 16 },
|
Package() { 0x0010FFFF, 1, 0, 17 },
|
Package() { 0x0010FFFF, 2, 0, 18 },
|
Package() { 0x0010FFFF, 3, 0, 19 },
|
// [CHD7]: Uncore 13 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, 0, 16 },
|
Package() { 0x0011FFFF, 1, 0, 17 },
|
Package() { 0x0011FFFF, 2, 0, 18 },
|
Package() { 0x0011FFFF, 3, 0, 19 },
|
// [CM12]: Uncore 13 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, 0, 16 },
|
Package() { 0x0014FFFF, 1, 0, 17 },
|
Package() { 0x0014FFFF, 2, 0, 18 },
|
Package() { 0x0014FFFF, 3, 0, 19 },
|
// [CM13]: Uncore 13 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, 0, 16 },
|
Package() { 0x0015FFFF, 1, 0, 17 },
|
Package() { 0x0015FFFF, 2, 0, 18 },
|
Package() { 0x0015FFFF, 3, 0, 19 },
|
// [CM14]: Uncore 13 CMS0CHA16-23 Device
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [CM15]: Uncore 13 CMS0CHA24-27 Device
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
// [CDL3]: Uncore 13 CHASADALL Device
|
Package() { 0x001DFFFF, 0, 0, 16 },
|
Package() { 0x001DFFFF, 1, 0, 17 },
|
Package() { 0x001DFFFF, 2, 0, 18 },
|
Package() { 0x001DFFFF, 3, 0, 19 },
|
// [PCU3]: Uncore 13 PCUCR Devices
|
Package() { 0x001EFFFF, 0, 0, 16 },
|
Package() { 0x001EFFFF, 1, 0, 17 },
|
Package() { 0x001EFFFF, 2, 0, 18 },
|
Package() { 0x001EFFFF, 3, 0, 19 },
|
// [VCU3]: Uncore 13 VCUCR Device
|
Package() { 0x001FFFFF, 0, 0, 16 },
|
Package() { 0x001FFFFF, 1, 0, 17 },
|
Package() { 0x001FFFFF, 2, 0, 18 },
|
Package() { 0x001FFFFF, 3, 0, 19 },
|
})
|
|
Name (AH59, Package() {
|
// [SR1A]: PCI Express Port 1A on PC19
|
Package() { 0x0000FFFF, 0, 0, 183 },
|
// [SR1B]: PCI Express Port 1B on PC19
|
Package() { 0x0001FFFF, 0, 0, 183 },
|
// [SR1C]: PCI Express Port 1C on PC19
|
Package() { 0x0002FFFF, 0, 0, 183 },
|
// [SR1D]: PCI Express Port 1D on PC19
|
Package() { 0x0003FFFF, 0, 0, 183 },
|
// [CHD0]: Uncore 13 CHAUTIL0-7 Device
|
Package() { 0x0008FFFF, 0, 0, 176 },
|
Package() { 0x0008FFFF, 1, 0, 180 },
|
Package() { 0x0008FFFF, 2, 0, 181 },
|
Package() { 0x0008FFFF, 3, 0, 182 },
|
// [CHD1]: Uncore 13 CHAUTIL8-15 Device
|
Package() { 0x0009FFFF, 0, 0, 176 },
|
Package() { 0x0009FFFF, 1, 0, 180 },
|
Package() { 0x0009FFFF, 2, 0, 181 },
|
Package() { 0x0009FFFF, 3, 0, 182 },
|
// [CHD2]: Uncore 13 CHAUTIL16-23 Device
|
Package() { 0x000AFFFF, 0, 0, 176 },
|
Package() { 0x000AFFFF, 1, 0, 180 },
|
Package() { 0x000AFFFF, 2, 0, 181 },
|
Package() { 0x000AFFFF, 3, 0, 182 },
|
// [CHD3]: Uncore 13 CHAUTIL24-27 Device
|
Package() { 0x000BFFFF, 0, 0, 176 },
|
Package() { 0x000BFFFF, 1, 0, 180 },
|
Package() { 0x000BFFFF, 2, 0, 181 },
|
Package() { 0x000BFFFF, 3, 0, 182 },
|
// [CHD4]: Uncore 13 CHASAD0-7 Device
|
Package() { 0x000EFFFF, 0, 0, 176 },
|
Package() { 0x000EFFFF, 1, 0, 180 },
|
Package() { 0x000EFFFF, 2, 0, 181 },
|
Package() { 0x000EFFFF, 3, 0, 182 },
|
// [CHD5]: Uncore 13 CHASAD8-15 Device
|
Package() { 0x000FFFFF, 0, 0, 176 },
|
Package() { 0x000FFFFF, 1, 0, 180 },
|
Package() { 0x000FFFFF, 2, 0, 181 },
|
Package() { 0x000FFFFF, 3, 0, 182 },
|
// [CHD6]: Uncore 13 CHASAD16-23 Device
|
Package() { 0x0010FFFF, 0, 0, 176 },
|
Package() { 0x0010FFFF, 1, 0, 180 },
|
Package() { 0x0010FFFF, 2, 0, 181 },
|
Package() { 0x0010FFFF, 3, 0, 182 },
|
// [CHD7]: Uncore 13 CHASAD24-27 Device
|
Package() { 0x0011FFFF, 0, 0, 176 },
|
Package() { 0x0011FFFF, 1, 0, 180 },
|
Package() { 0x0011FFFF, 2, 0, 181 },
|
Package() { 0x0011FFFF, 3, 0, 182 },
|
// [CM12]: Uncore 13 CMSCHA0-7 Device
|
Package() { 0x0014FFFF, 0, 0, 176 },
|
Package() { 0x0014FFFF, 1, 0, 180 },
|
Package() { 0x0014FFFF, 2, 0, 181 },
|
Package() { 0x0014FFFF, 3, 0, 182 },
|
// [CM13]: Uncore 13 CMS0CHA8-15 Device
|
Package() { 0x0015FFFF, 0, 0, 176 },
|
Package() { 0x0015FFFF, 1, 0, 180 },
|
Package() { 0x0015FFFF, 2, 0, 181 },
|
Package() { 0x0015FFFF, 3, 0, 182 },
|
// [CM14]: Uncore 13 CMS0CHA16-23 Device
|
Package() { 0x0016FFFF, 0, 0, 176 },
|
Package() { 0x0016FFFF, 1, 0, 180 },
|
Package() { 0x0016FFFF, 2, 0, 181 },
|
Package() { 0x0016FFFF, 3, 0, 182 },
|
// [CM15]: Uncore 13 CMS0CHA24-27 Device
|
Package() { 0x0017FFFF, 0, 0, 176 },
|
Package() { 0x0017FFFF, 1, 0, 180 },
|
Package() { 0x0017FFFF, 2, 0, 181 },
|
Package() { 0x0017FFFF, 3, 0, 182 },
|
// [CDL3]: Uncore 13 CHASADALL Device
|
Package() { 0x001DFFFF, 0, 0, 176 },
|
Package() { 0x001DFFFF, 1, 0, 180 },
|
Package() { 0x001DFFFF, 2, 0, 181 },
|
Package() { 0x001DFFFF, 3, 0, 182 },
|
// [PCU3]: Uncore 13 PCUCR Devices
|
Package() { 0x001EFFFF, 0, 0, 176 },
|
Package() { 0x001EFFFF, 1, 0, 180 },
|
Package() { 0x001EFFFF, 2, 0, 181 },
|
Package() { 0x001EFFFF, 3, 0, 182 },
|
// [VCU3]: Uncore 13 VCUCR Device
|
Package() { 0x001FFFFF, 0, 0, 176 },
|
Package() { 0x001FFFFF, 1, 0, 180 },
|
Package() { 0x001FFFFF, 2, 0, 181 },
|
Package() { 0x001FFFFF, 3, 0, 182 },
|
})
|
|
Name (PR5A, Package() {
|
// [SL2E]: PCI Express Slot 46 on 1A on PC19
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR5A, Package() {
|
// [SL2E]: PCI Express Slot 46 on 1A on PC19
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH5A, Package() {
|
// [SL2E]: PCI Express Slot 46 on 1A on PC19
|
Package() { 0x0000FFFF, 0, 0, 176 },
|
Package() { 0x0000FFFF, 1, 0, 180 },
|
Package() { 0x0000FFFF, 2, 0, 181 },
|
Package() { 0x0000FFFF, 3, 0, 182 },
|
})
|
|
Name (PR5B, Package() {
|
// [SL2F]: PCI Express Slot 47 on 1B on PC19
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR5B, Package() {
|
// [SL2F]: PCI Express Slot 47 on 1B on PC19
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH5B, Package() {
|
// [SL2F]: PCI Express Slot 47 on 1B on PC19
|
Package() { 0x0000FFFF, 0, 0, 177 },
|
Package() { 0x0000FFFF, 1, 0, 182 },
|
Package() { 0x0000FFFF, 2, 0, 180 },
|
Package() { 0x0000FFFF, 3, 0, 181 },
|
})
|
|
Name (PR5C, Package() {
|
// [SL30]: PCI Express Slot 48 on 1C on PC19
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR5C, Package() {
|
// [SL30]: PCI Express Slot 48 on 1C on PC19
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH5C, Package() {
|
// [SL30]: PCI Express Slot 48 on 1C on PC19
|
Package() { 0x0000FFFF, 0, 0, 178 },
|
Package() { 0x0000FFFF, 1, 0, 181 },
|
Package() { 0x0000FFFF, 2, 0, 182 },
|
Package() { 0x0000FFFF, 3, 0, 180 },
|
})
|
|
Name (PR5D, Package() {
|
// [SL31]: PCI Express Slot 49 on 1D on PC19
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR5D, Package() {
|
// [SL31]: PCI Express Slot 49 on 1D on PC19
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH5D, Package() {
|
// [SL31]: PCI Express Slot 49 on 1D on PC19
|
Package() { 0x0000FFFF, 0, 0, 179 },
|
Package() { 0x0000FFFF, 1, 0, 182 },
|
Package() { 0x0000FFFF, 2, 0, 180 },
|
Package() { 0x0000FFFF, 3, 0, 181 },
|
})
|
|
Name (PR5E, Package() {
|
// [SR2A]: PCI Express Port 2A on PC20
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [SR2B]: PCI Express Port 2B on PC20
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [SR2C]: PCI Express Port 2C on PC20
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [SR2D]: PCI Express Port 2D on PC20
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [M2M6]: Uncore 14 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2M7]: Uncore 14 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCM6]: Uncore 14 MCMAIN Device
|
Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCD6]: Uncore 14 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCM7]: Uncore 14 MCMAIN Device
|
Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [MCD7]: Uncore 14 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR5E, Package() {
|
// [SR2A]: PCI Express Port 2A on PC20
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [SR2B]: PCI Express Port 2B on PC20
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [SR2C]: PCI Express Port 2C on PC20
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [SR2D]: PCI Express Port 2D on PC20
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [M2M6]: Uncore 14 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, 0, 16 },
|
Package() { 0x0008FFFF, 1, 0, 17 },
|
Package() { 0x0008FFFF, 2, 0, 18 },
|
Package() { 0x0008FFFF, 3, 0, 19 },
|
// [M2M7]: Uncore 14 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, 0, 16 },
|
Package() { 0x0009FFFF, 1, 0, 17 },
|
Package() { 0x0009FFFF, 2, 0, 18 },
|
Package() { 0x0009FFFF, 3, 0, 19 },
|
// [MCM6]: Uncore 14 MCMAIN Device
|
Package() { 0x000AFFFF, 0, 0, 16 },
|
Package() { 0x000AFFFF, 1, 0, 17 },
|
Package() { 0x000AFFFF, 2, 0, 18 },
|
Package() { 0x000AFFFF, 3, 0, 19 },
|
// [MCD6]: Uncore 14 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, 0, 16 },
|
Package() { 0x000BFFFF, 1, 0, 17 },
|
Package() { 0x000BFFFF, 2, 0, 18 },
|
Package() { 0x000BFFFF, 3, 0, 19 },
|
// [MCM7]: Uncore 14 MCMAIN Device
|
Package() { 0x000CFFFF, 0, 0, 16 },
|
Package() { 0x000CFFFF, 1, 0, 17 },
|
Package() { 0x000CFFFF, 2, 0, 18 },
|
Package() { 0x000CFFFF, 3, 0, 19 },
|
// [MCD7]: Uncore 14 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, 0, 16 },
|
Package() { 0x000DFFFF, 1, 0, 17 },
|
Package() { 0x000DFFFF, 2, 0, 18 },
|
Package() { 0x000DFFFF, 3, 0, 19 },
|
// [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
})
|
|
Name (AH5E, Package() {
|
// [SR2A]: PCI Express Port 2A on PC20
|
Package() { 0x0000FFFF, 0, 0, 191 },
|
// [SR2B]: PCI Express Port 2B on PC20
|
Package() { 0x0001FFFF, 0, 0, 191 },
|
// [SR2C]: PCI Express Port 2C on PC20
|
Package() { 0x0002FFFF, 0, 0, 191 },
|
// [SR2D]: PCI Express Port 2D on PC20
|
Package() { 0x0003FFFF, 0, 0, 191 },
|
// [M2M6]: Uncore 14 M2MEM0 Device
|
Package() { 0x0008FFFF, 0, 0, 184 },
|
Package() { 0x0008FFFF, 1, 0, 188 },
|
Package() { 0x0008FFFF, 2, 0, 189 },
|
Package() { 0x0008FFFF, 3, 0, 190 },
|
// [M2M7]: Uncore 14 M2MEM10 Device
|
Package() { 0x0009FFFF, 0, 0, 184 },
|
Package() { 0x0009FFFF, 1, 0, 188 },
|
Package() { 0x0009FFFF, 2, 0, 189 },
|
Package() { 0x0009FFFF, 3, 0, 190 },
|
// [MCM6]: Uncore 14 MCMAIN Device
|
Package() { 0x000AFFFF, 0, 0, 184 },
|
Package() { 0x000AFFFF, 1, 0, 188 },
|
Package() { 0x000AFFFF, 2, 0, 189 },
|
Package() { 0x000AFFFF, 3, 0, 190 },
|
// [MCD6]: Uncore 14 MCDECS2 Device
|
Package() { 0x000BFFFF, 0, 0, 184 },
|
Package() { 0x000BFFFF, 1, 0, 188 },
|
Package() { 0x000BFFFF, 2, 0, 189 },
|
Package() { 0x000BFFFF, 3, 0, 190 },
|
// [MCM7]: Uncore 14 MCMAIN Device
|
Package() { 0x000CFFFF, 0, 0, 184 },
|
Package() { 0x000CFFFF, 1, 0, 188 },
|
Package() { 0x000CFFFF, 2, 0, 189 },
|
Package() { 0x000CFFFF, 3, 0, 190 },
|
// [MCD7]: Uncore 14 MCDECS12 Device
|
Package() { 0x000DFFFF, 0, 0, 184 },
|
Package() { 0x000DFFFF, 1, 0, 188 },
|
Package() { 0x000DFFFF, 2, 0, 189 },
|
Package() { 0x000DFFFF, 3, 0, 190 },
|
// [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device
|
Package() { 0x0016FFFF, 0, 0, 184 },
|
Package() { 0x0016FFFF, 1, 0, 188 },
|
Package() { 0x0016FFFF, 2, 0, 189 },
|
Package() { 0x0016FFFF, 3, 0, 190 },
|
// [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device
|
Package() { 0x0017FFFF, 0, 0, 184 },
|
Package() { 0x0017FFFF, 1, 0, 188 },
|
Package() { 0x0017FFFF, 2, 0, 189 },
|
Package() { 0x0017FFFF, 3, 0, 190 },
|
})
|
|
Name (PR5F, Package() {
|
// [SL32]: PCI Express Slot 50 on 2A on PC20
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR5F, Package() {
|
// [SL32]: PCI Express Slot 50 on 2A on PC20
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH5F, Package() {
|
// [SL32]: PCI Express Slot 50 on 2A on PC20
|
Package() { 0x0000FFFF, 0, 0, 184 },
|
Package() { 0x0000FFFF, 1, 0, 188 },
|
Package() { 0x0000FFFF, 2, 0, 189 },
|
Package() { 0x0000FFFF, 3, 0, 190 },
|
})
|
|
Name (PR60, Package() {
|
// [SL33]: PCI Express Slot 51 on 2B on PC20
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR60, Package() {
|
// [SL33]: PCI Express Slot 51 on 2B on PC20
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH60, Package() {
|
// [SL33]: PCI Express Slot 51 on 2B on PC20
|
Package() { 0x0000FFFF, 0, 0, 185 },
|
Package() { 0x0000FFFF, 1, 0, 190 },
|
Package() { 0x0000FFFF, 2, 0, 188 },
|
Package() { 0x0000FFFF, 3, 0, 189 },
|
})
|
|
Name (PR61, Package() {
|
// [SL34]: PCI Express Slot 52 on 2C on PC20
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR61, Package() {
|
// [SL34]: PCI Express Slot 52 on 2C on PC20
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH61, Package() {
|
// [SL34]: PCI Express Slot 52 on 2C on PC20
|
Package() { 0x0000FFFF, 0, 0, 186 },
|
Package() { 0x0000FFFF, 1, 0, 189 },
|
Package() { 0x0000FFFF, 2, 0, 190 },
|
Package() { 0x0000FFFF, 3, 0, 188 },
|
})
|
|
Name (PR62, Package() {
|
// [SL35]: PCI Express Slot 53 on 2D on PC20
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR62, Package() {
|
// [SL35]: PCI Express Slot 53 on 2D on PC20
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH62, Package() {
|
// [SL35]: PCI Express Slot 53 on 2D on PC20
|
Package() { 0x0000FFFF, 0, 0, 187 },
|
Package() { 0x0000FFFF, 1, 0, 190 },
|
Package() { 0x0000FFFF, 2, 0, 188 },
|
Package() { 0x0000FFFF, 3, 0, 189 },
|
})
|
|
Name (PR63, Package() {
|
// [SR3A]: PCI Express Port 3A on PC21
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [SR3B]: PCI Express Port 3B on PC21
|
Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [SR3C]: PCI Express Port 3C on PC21
|
Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [SR3D]: PCI Express Port 3D on PC21
|
Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
// [KTI9]: Uncore 15 KTI9
|
Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [KT10]: Uncore 15 KT10
|
Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [KT11]: Uncore 15 KT11
|
Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M3K3]: Uncore 15 M3K3
|
Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2U3]: Uncore 15 M2U3
|
Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M2D3]: Uncore 15 M2D3
|
Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
// [M23]: Uncore 15 M23
|
Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR63, Package() {
|
// [SR3A]: PCI Express Port 3A on PC21
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
// [SR3B]: PCI Express Port 3B on PC21
|
Package() { 0x0001FFFF, 0, 0, 16 },
|
// [SR3C]: PCI Express Port 3C on PC21
|
Package() { 0x0002FFFF, 0, 0, 16 },
|
// [SR3D]: PCI Express Port 3D on PC21
|
Package() { 0x0003FFFF, 0, 0, 16 },
|
// [KTI9]: Uncore 15 KTI9
|
Package() { 0x000EFFFF, 0, 0, 16 },
|
Package() { 0x000EFFFF, 1, 0, 17 },
|
Package() { 0x000EFFFF, 2, 0, 18 },
|
Package() { 0x000EFFFF, 3, 0, 19 },
|
// [KT10]: Uncore 15 KT10
|
Package() { 0x000FFFFF, 0, 0, 16 },
|
Package() { 0x000FFFFF, 1, 0, 17 },
|
Package() { 0x000FFFFF, 2, 0, 18 },
|
Package() { 0x000FFFFF, 3, 0, 19 },
|
// [KT11]: Uncore 15 KT11
|
Package() { 0x0010FFFF, 0, 0, 16 },
|
Package() { 0x0010FFFF, 1, 0, 17 },
|
Package() { 0x0010FFFF, 2, 0, 18 },
|
Package() { 0x0010FFFF, 3, 0, 19 },
|
// [M3K3]: Uncore 15 M3K3
|
Package() { 0x0012FFFF, 0, 0, 16 },
|
Package() { 0x0012FFFF, 1, 0, 17 },
|
Package() { 0x0012FFFF, 2, 0, 18 },
|
Package() { 0x0012FFFF, 3, 0, 19 },
|
// [M2U3]: Uncore 15 M2U3
|
Package() { 0x0015FFFF, 0, 0, 16 },
|
Package() { 0x0015FFFF, 1, 0, 17 },
|
Package() { 0x0015FFFF, 2, 0, 18 },
|
Package() { 0x0015FFFF, 3, 0, 19 },
|
// [M2D3]: Uncore 15 M2D3
|
Package() { 0x0016FFFF, 0, 0, 16 },
|
Package() { 0x0016FFFF, 1, 0, 17 },
|
Package() { 0x0016FFFF, 2, 0, 18 },
|
Package() { 0x0016FFFF, 3, 0, 19 },
|
// [M23]: Uncore 15 M23
|
Package() { 0x0017FFFF, 0, 0, 16 },
|
Package() { 0x0017FFFF, 1, 0, 17 },
|
Package() { 0x0017FFFF, 2, 0, 18 },
|
Package() { 0x0017FFFF, 3, 0, 19 },
|
})
|
|
Name (AH63, Package() {
|
// [SR3A]: PCI Express Port 3A on PC21
|
Package() { 0x0000FFFF, 0, 0, 199 },
|
// [SR3B]: PCI Express Port 3B on PC21
|
Package() { 0x0001FFFF, 0, 0, 199 },
|
// [SR3C]: PCI Express Port 3C on PC21
|
Package() { 0x0002FFFF, 0, 0, 199 },
|
// [SR3D]: PCI Express Port 3D on PC21
|
Package() { 0x0003FFFF, 0, 0, 199 },
|
// [KTI9]: Uncore 15 KTI9
|
Package() { 0x000EFFFF, 0, 0, 192 },
|
Package() { 0x000EFFFF, 1, 0, 196 },
|
Package() { 0x000EFFFF, 2, 0, 197 },
|
Package() { 0x000EFFFF, 3, 0, 198 },
|
// [KT10]: Uncore 15 KT10
|
Package() { 0x000FFFFF, 0, 0, 192 },
|
Package() { 0x000FFFFF, 1, 0, 196 },
|
Package() { 0x000FFFFF, 2, 0, 197 },
|
Package() { 0x000FFFFF, 3, 0, 198 },
|
// [KT11]: Uncore 15 KT11
|
Package() { 0x0010FFFF, 0, 0, 192 },
|
Package() { 0x0010FFFF, 1, 0, 196 },
|
Package() { 0x0010FFFF, 2, 0, 197 },
|
Package() { 0x0010FFFF, 3, 0, 198 },
|
// [M3K3]: Uncore 15 M3K3
|
Package() { 0x0012FFFF, 0, 0, 192 },
|
Package() { 0x0012FFFF, 1, 0, 196 },
|
Package() { 0x0012FFFF, 2, 0, 197 },
|
Package() { 0x0012FFFF, 3, 0, 198 },
|
// [M2U3]: Uncore 15 M2U3
|
Package() { 0x0015FFFF, 0, 0, 192 },
|
Package() { 0x0015FFFF, 1, 0, 196 },
|
Package() { 0x0015FFFF, 2, 0, 197 },
|
Package() { 0x0015FFFF, 3, 0, 198 },
|
// [M2D3]: Uncore 15 M2D3
|
Package() { 0x0016FFFF, 0, 0, 192 },
|
Package() { 0x0016FFFF, 1, 0, 196 },
|
Package() { 0x0016FFFF, 2, 0, 197 },
|
Package() { 0x0016FFFF, 3, 0, 198 },
|
// [M23]: Uncore 15 M23
|
Package() { 0x0017FFFF, 0, 0, 192 },
|
Package() { 0x0017FFFF, 1, 0, 196 },
|
Package() { 0x0017FFFF, 2, 0, 197 },
|
Package() { 0x0017FFFF, 3, 0, 198 },
|
})
|
|
Name (PR64, Package() {
|
// [SL36]: PCI Express Slot 54 on 3A on PC21
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR64, Package() {
|
// [SL36]: PCI Express Slot 54 on 3A on PC21
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH64, Package() {
|
// [SL36]: PCI Express Slot 54 on 3A on PC21
|
Package() { 0x0000FFFF, 0, 0, 192 },
|
Package() { 0x0000FFFF, 1, 0, 196 },
|
Package() { 0x0000FFFF, 2, 0, 197 },
|
Package() { 0x0000FFFF, 3, 0, 198 },
|
})
|
|
Name (PR65, Package() {
|
// [SL37]: PCI Express Slot 55 on 3B on PC21
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR65, Package() {
|
// [SL37]: PCI Express Slot 55 on 3B on PC21
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH65, Package() {
|
// [SL37]: PCI Express Slot 55 on 3B on PC21
|
Package() { 0x0000FFFF, 0, 0, 193 },
|
Package() { 0x0000FFFF, 1, 0, 198 },
|
Package() { 0x0000FFFF, 2, 0, 196 },
|
Package() { 0x0000FFFF, 3, 0, 197 },
|
})
|
|
Name (PR66, Package() {
|
// [SL38]: PCI Express Slot 56 on 3C on PC21
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR66, Package() {
|
// [SL38]: PCI Express Slot 56 on 3C on PC21
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH66, Package() {
|
// [SL38]: PCI Express Slot 56 on 3C on PC21
|
Package() { 0x0000FFFF, 0, 0, 194 },
|
Package() { 0x0000FFFF, 1, 0, 197 },
|
Package() { 0x0000FFFF, 2, 0, 198 },
|
Package() { 0x0000FFFF, 3, 0, 196 },
|
})
|
|
Name (PR67, Package() {
|
// [SL39]: PCI Express Slot 57 on 3D on PC21
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR67, Package() {
|
// [SL39]: PCI Express Slot 57 on 3D on PC21
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH67, Package() {
|
// [SL39]: PCI Express Slot 57 on 3D on PC21
|
Package() { 0x0000FFFF, 0, 0, 195 },
|
Package() { 0x0000FFFF, 1, 0, 198 },
|
Package() { 0x0000FFFF, 2, 0, 196 },
|
Package() { 0x0000FFFF, 3, 0, 197 },
|
})
|
|
Name (PR68, Package() {
|
// [MCP6]: PCI Express Port 4 on PC22
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR68, Package() {
|
// [MCP6]: PCI Express Port 4 on PC22
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH68, Package() {
|
// [MCP6]: PCI Express Port 4 on PC22
|
Package() { 0x0000FFFF, 0, 0, 207 },
|
})
|
|
Name (PR69, Package() {
|
// [SL3A]: PCI Express Slot 58 on 4 on PC22
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR69, Package() {
|
// [SL3A]: PCI Express Slot 58 on 4 on PC22
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH69, Package() {
|
// [SL3A]: PCI Express Slot 58 on 4 on PC22
|
Package() { 0x0000FFFF, 0, 0, 200 },
|
Package() { 0x0000FFFF, 1, 0, 204 },
|
Package() { 0x0000FFFF, 2, 0, 205 },
|
Package() { 0x0000FFFF, 3, 0, 206 },
|
})
|
|
Name (PR6A, Package() {
|
// [MCP7]: PCI Express Port 5 on PC23
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR6A, Package() {
|
// [MCP7]: PCI Express Port 5 on PC23
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (AH6A, Package() {
|
// [MCP7]: PCI Express Port 5 on PC23
|
Package() { 0x0000FFFF, 0, 0, 215 },
|
})
|
|
Name (PR6B, Package() {
|
// [SL3B]: PCI Express Slot 59 on 4 on PC23
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR6B, Package() {
|
// [SL3B]: PCI Express Slot 59 on 4 on PC23
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (AH6B, Package() {
|
// [SL3B]: PCI Express Slot 59 on 4 on PC23
|
Package() { 0x0000FFFF, 0, 0, 208 },
|
Package() { 0x0000FFFF, 1, 0, 212 },
|
Package() { 0x0000FFFF, 2, 0, 213 },
|
Package() { 0x0000FFFF, 3, 0, 214 },
|
})
|
|
Name (PR6C, Package() {
|
// [FPG0]: FPGA Device
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR6C, Package() {
|
// [FPG0]: FPGA Device
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (PR6D, Package() {
|
// [FPG1]: FPGA Device
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
})
|
|
Name (AR6D, Package() {
|
// [FPG1]: FPGA Device
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
})
|
|
Name (PR6E, Package() {
|
// [FPG2]: FPGA Device
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
})
|
|
Name (AR6E, Package() {
|
// [FPG2]: FPGA Device
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
})
|
|
Name (PR6F, Package() {
|
// [FPG3]: FPGA Device
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR6F, Package() {
|
// [FPG3]: FPGA Device
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
Name (PR70, Package() {
|
// [FKT0]: FPGA Device
|
Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
|
})
|
|
Name (AR70, Package() {
|
// [FKT0]: FPGA Device
|
Package() { 0x0000FFFF, 0, 0, 16 },
|
})
|
|
Name (PR71, Package() {
|
// [FKT1]: FPGA Device
|
Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
|
})
|
|
Name (AR71, Package() {
|
// [FKT1]: FPGA Device
|
Package() { 0x0000FFFF, 1, 0, 17 },
|
})
|
|
Name (PR72, Package() {
|
// [FKT2]: FPGA Device
|
Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
|
})
|
|
Name (AR72, Package() {
|
// [FKT2]: FPGA Device
|
Package() { 0x0000FFFF, 2, 0, 18 },
|
})
|
|
Name (PR73, Package() {
|
// [FKT3]: FPGA Device
|
Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
|
})
|
|
Name (AR73, Package() {
|
// [FKT3]: FPGA Device
|
Package() { 0x0000FFFF, 3, 0, 19 },
|
})
|
|
// Socket 0 Root bridge (Stack 0)
|
Device (PC00) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x00)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB00)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR00)
|
}
|
If (LEqual(AP00, One)) {
|
Return (AH00)
|
}
|
Return (AR00)
|
}
|
|
#include "PC00.asi"
|
#include "HostBus.asl"
|
|
// Legacy PCI Express Port 0 on PC00
|
Device (DMI0) {
|
Name (_ADR, 0x00000000)
|
}
|
|
// CB3DMA on PC00
|
Device (CB0A) {
|
Name (_ADR, 0x00040000)
|
}
|
|
// CB3DMA on PC00
|
Device (CB0B) {
|
Name (_ADR, 0x00040001)
|
}
|
|
// CB3DMA on PC00
|
Device (CB0C) {
|
Name (_ADR, 0x00040002)
|
}
|
|
// CB3DMA on PC00
|
Device (CB0D) {
|
Name (_ADR, 0x00040003)
|
}
|
|
// CB3DMA on PC00
|
Device (CB0E) {
|
Name (_ADR, 0x00040004)
|
}
|
|
// CB3DMA on PC00
|
Device (CB0F) {
|
Name (_ADR, 0x00040005)
|
}
|
|
// CB3DMA on PC00
|
Device (CB0G) {
|
Name (_ADR, 0x00040006)
|
}
|
|
// CB3DMA on PC00
|
Device (CB0H) {
|
Name (_ADR, 0x00040007)
|
}
|
|
// IIOMISC on PC00
|
Device (IIM0) {
|
Name (_ADR, 0x00050000)
|
}
|
|
// Uncore 0 UBOX Device
|
Device (UBX0) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// High definition Audio Controller
|
Device (ALZA) {
|
Name (_ADR, 0x000E0000)
|
}
|
|
// Display Controller
|
Device (DISP) {
|
Name (_ADR, 0x000F0000)
|
}
|
|
// HECI #1
|
Device (IHC1) {
|
Name (_ADR, 0x00100000)
|
}
|
|
// HECI #2
|
Device (IHC2) {
|
Name (_ADR, 0x00100001)
|
}
|
|
// IDE-Redirection (IDE-R)
|
Device (IIDR) {
|
Name (_ADR, 0x00100002)
|
}
|
|
// Keyboard and Text (KT) Redirection
|
Device (IMKT) {
|
Name (_ADR, 0x00100003)
|
}
|
|
// HECI #3
|
Device (IHC3) {
|
Name (_ADR, 0x00100004)
|
}
|
|
// MROM 0 function function
|
Device (MRO0) {
|
Name (_ADR, 0x00110000)
|
}
|
|
// MROM 1 function function
|
Device (MRO1) {
|
Name (_ADR, 0x00110001)
|
}
|
|
// sSATA Host controller 2 on PCH
|
Device (SAT2) {
|
Name (_ADR, 0x00110005)
|
}
|
|
// xHCI controller 1 on PCH
|
Device (XHCI) {
|
Name (_ADR, 0x00140000)
|
}
|
|
// USB Device Controller (OTG) on PCH
|
Device (OTG0) {
|
Name (_ADR, 0x00140001)
|
}
|
|
// Thermal Subsystem on PCH
|
Device (TERM) {
|
Name (_ADR, 0x00140002)
|
}
|
|
// Camera IO Host Controller on PCH
|
Device (CAMR) {
|
Name (_ADR, 0x00140003)
|
}
|
|
// Northpeak Phantom (ACPI) Function on PCH
|
Device (NTHP) {
|
Name (_ADR, 0x00140004)
|
}
|
|
// HECI #1 on PCH
|
Device (HEC1) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// HECI #2 on PCH
|
Device (HEC2) {
|
Name (_ADR, 0x00160001)
|
}
|
|
// ME IDE redirect on PCH
|
Device (IDER) {
|
Name (_ADR, 0x00160002)
|
}
|
|
// MEKT on PCH
|
Device (MEKT) {
|
Name (_ADR, 0x00160003)
|
}
|
|
// HECI #3 on PCH
|
Device (HEC3) {
|
Name (_ADR, 0x00160004)
|
}
|
|
// SATA controller 1 on PCH
|
Device (SAT1) {
|
Name (_ADR, 0x00170000)
|
}
|
|
// NAND Cycle Router on PCH
|
Device (NAN1) {
|
Name (_ADR, 0x00180000)
|
}
|
|
// PCIE PCH Root Port #17
|
Device (RP17) {
|
#include "RP17_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR01)
|
}
|
Return (AR01)
|
}
|
|
// PCIE PCH Slot #17
|
Device (SLTH) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #18
|
Device (RP18) {
|
#include "RP18_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR02)
|
}
|
Return (AR02)
|
}
|
|
// PCIE PCH Slot #18
|
Device (SLTI) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #19
|
Device (RP19) {
|
#include "RP19_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR03)
|
}
|
Return (AR03)
|
}
|
|
// PCIE PCH Slot #19
|
Device (SLTJ) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #20
|
Device (RP20) {
|
#include "RP20_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR04)
|
}
|
Return (AR04)
|
}
|
|
// PCIE PCH Slot #20
|
Device (SLTK) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #1
|
Device (RP01) {
|
#include "RP01_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR05)
|
}
|
Return (AR05)
|
}
|
}
|
|
// PCIE PCH Root Port #2
|
Device (RP02) {
|
#include "RP02_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR06)
|
}
|
Return (AR06)
|
}
|
}
|
|
// PCIE PCH Root Port #3
|
Device (RP03) {
|
#include "RP03_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR07)
|
}
|
Return (AR07)
|
}
|
}
|
|
// PCIE PCH Root Port #4
|
Device (RP04) {
|
#include "RP04_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR08)
|
}
|
Return (AR08)
|
}
|
}
|
|
// PCIE PCH Root Port #5
|
Device (RP05) {
|
#include "RP05_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR09)
|
}
|
Return (AR09)
|
}
|
}
|
|
// PCIE PCH Root Port #6
|
Device (RP06) {
|
#include "RP06_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR0A)
|
}
|
Return (AR0A)
|
}
|
}
|
|
// PCIE PCH Root Port #7
|
Device (RP07) {
|
#include "RP07_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR0B)
|
}
|
Return (AR0B)
|
}
|
}
|
|
// PCIE PCH Root Port #8
|
Device (RP08) {
|
#include "RP08_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR0C)
|
}
|
Return (AR0C)
|
}
|
}
|
|
// PCIE PCH Root Port #9
|
Device (RP09) {
|
#include "RP09_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR0D)
|
}
|
Return (AR0D)
|
}
|
|
// PCIE PCH Slot #9
|
Device (SLT9) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #10
|
Device (RP10) {
|
#include "RP10_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR0E)
|
}
|
Return (AR0E)
|
}
|
|
// PCIE PCH Slot #10
|
Device (SLTA) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #11
|
Device (RP11) {
|
#include "RP11_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR0F)
|
}
|
Return (AR0F)
|
}
|
|
// PCIE PCH Slot #11
|
Device (SLTB) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #12
|
Device (RP12) {
|
#include "RP12_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR10)
|
}
|
Return (AR10)
|
}
|
|
// PCIE PCH Slot #12
|
Device (SLTC) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #13
|
Device (RP13) {
|
#include "RP13_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR11)
|
}
|
Return (AR11)
|
}
|
|
// PCIE PCH Slot #13
|
Device (SLTD) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #14
|
Device (RP14) {
|
#include "RP14_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR12)
|
}
|
Return (AR12)
|
}
|
|
// PCIE PCH Slot #14
|
Device (SLTE) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #15
|
Device (RP15) {
|
#include "RP15_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR13)
|
}
|
Return (AR13)
|
}
|
|
// PCIE PCH Slot #15
|
Device (SLTF) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// PCIE PCH Root Port #16
|
Device (RP16) {
|
#include "RP16_ADR.asl"
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR14)
|
}
|
Return (AR14)
|
}
|
|
// PCIE PCH Slot #16
|
Device (SLTG) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// UART #0 on PCH
|
Device (UAR0) {
|
Name (_ADR, 0x001E0000)
|
}
|
|
// UART #1 on PCH
|
Device (UAR1) {
|
Name (_ADR, 0x001E0001)
|
}
|
|
// SPI #0 on PCH
|
Device (SPI0) {
|
Name (_ADR, 0x001E0002)
|
}
|
|
// SPI #1 on PCH
|
Device (SPI1) {
|
Name (_ADR, 0x001E0003)
|
}
|
|
// ISA Bridge on PCH
|
Device (LPC0) {
|
Name (_ADR, 0x001F0000)
|
|
#include "PchLpc.asi"
|
}
|
|
// Power Management Controller on PCH
|
Device (PMC1) {
|
Name (_ADR, 0x001F0002)
|
}
|
|
// HD Audio Subsystem Controller on PCH
|
Device (CAVS) {
|
Name (_ADR, 0x001F0003)
|
}
|
|
// SMBus controller on PCH
|
Device (SMBS) {
|
Name (_ADR, 0x001F0004)
|
}
|
|
// SPI controller on PCH
|
Device (SPIC) {
|
Name (_ADR, 0x001F0005)
|
}
|
|
// GbE Controller on PCH
|
Device (GBE1) {
|
Name (_ADR, 0x001F0006)
|
}
|
|
// Northpeak Controller on PCH
|
Device (NTPK) {
|
Name (_ADR, 0x001F0007)
|
}
|
}
|
|
// Socket 0 Root bridge (Stack 1)
|
Device (PC01) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x01)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB01)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR15)
|
}
|
If (LEqual(AP01, One)) {
|
Return (AH15)
|
}
|
Return (AR15)
|
}
|
|
#include "PC01.asi"
|
|
// PCI Express Port 1A on PC01
|
Device (BR1A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR16)
|
}
|
If (LEqual(AP01, One)) {
|
Return (AH16)
|
}
|
Return (AR16)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// PCI Express Port 1B on PC01
|
Device (BR1B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR17)
|
}
|
If (LEqual(AP01, One)) {
|
Return (AH17)
|
}
|
Return (AR17)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// PCI Express Port 1C on PC01
|
Device (BR1C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR18)
|
}
|
If (LEqual(AP01, One)) {
|
Return (AH18)
|
}
|
Return (AR18)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// PCI Express Port 1D on PC01
|
Device (BR1D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR19)
|
}
|
If (LEqual(AP01, One)) {
|
Return (AH19)
|
}
|
Return (AR19)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// Uncore 1 CHAUTIL0-7 Device
|
Device (CHA0) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// Uncore 1 CHAUTIL8-15 Device
|
Device (CHA1) {
|
Name (_ADR, 0x00090000)
|
}
|
|
// Uncore 1 CHAUTIL16-23 Device
|
Device (CHA2) {
|
Name (_ADR, 0x000A0000)
|
}
|
|
// Uncore 1 CHAUTIL24-27 Device
|
Device (CHA3) {
|
Name (_ADR, 0x000B0000)
|
}
|
|
// Uncore 1 CHASAD0-7 Device
|
Device (CHA4) {
|
Name (_ADR, 0x000E0000)
|
}
|
|
// Uncore 1 CHASAD8-15 Device
|
Device (CHA5) {
|
Name (_ADR, 0x000F0000)
|
}
|
|
// Uncore 1 CHASAD16-23 Device
|
Device (CHA6) {
|
Name (_ADR, 0x00100000)
|
}
|
|
// Uncore 1 CHASAD24-27 Device
|
Device (CHA7) {
|
Name (_ADR, 0x00110000)
|
}
|
|
// Uncore 1 CMSCHA0-7 Device
|
Device (CMS0) {
|
Name (_ADR, 0x00140000)
|
}
|
|
// Uncore 1 CMS0CHA8-15 Device
|
Device (CMS1) {
|
Name (_ADR, 0x00150000)
|
}
|
|
// Uncore 1 CMS0CHA16-23 Device
|
Device (CMS2) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 1 CMS0CHA24-27 Device
|
Device (CMS3) {
|
Name (_ADR, 0x00170000)
|
}
|
|
// Uncore 1 CHASADALL Device
|
Device (CDL0) {
|
Name (_ADR, 0x001D0000)
|
}
|
|
// Uncore 1 PCUCR Devices
|
Device (PCU0) {
|
Name (_ADR, 0x001E0000)
|
}
|
|
// Uncore 1 VCUCR Device
|
Device (VCU0) {
|
Name (_ADR, 0x001F0000)
|
}
|
}
|
|
// Socket 0 Root bridge (Stack 2)
|
Device (PC02) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x02)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB02)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR1A)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH1A)
|
}
|
Return (AR1A)
|
}
|
|
#include "PC02.asi"
|
|
// PCI Express Port 2A on PC02
|
Device (BR2A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR1B)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH1B)
|
}
|
Return (AR1B)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
|
// EVA PCIe Uplink
|
Device (EPCU) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x0B, 0x00})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR1C)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH1C)
|
}
|
Return (AR1C)
|
}
|
|
// EVA Virtual Switch Port 0
|
Device (VSP0) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x0B, 0x00})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR1D)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH1D)
|
}
|
Return (AR1D)
|
}
|
|
// EVA CPM0
|
Device (CPM0) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// EVA Virtual Switch Port 1
|
Device (VSP1) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x0B, 0x00})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR1E)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH1E)
|
}
|
Return (AR1E)
|
}
|
|
// EVA CPM1
|
Device (CPM1) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// EVA Virtual Switch Port 2
|
Device (VSP2) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x0B, 0x00})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR1F)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH1F)
|
}
|
Return (AR1F)
|
}
|
|
// EVA CPM2
|
Device (CPM2) {
|
Name (_ADR, 0x00000000)
|
}
|
}
|
|
// EVA Virtual Switch Port 3
|
Device (VSP3) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x0B, 0x00})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR20)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH20)
|
}
|
Return (AR20)
|
}
|
|
// EVA Fort Park 0
|
Device (FPK0) {
|
Name (_ADR, 0x00000000)
|
}
|
|
// EVA Fort Park 1
|
Device (FPK1) {
|
Name (_ADR, 0x00000001)
|
}
|
|
// EVA Fort Park 2
|
Device (FPK2) {
|
Name (_ADR, 0x00000002)
|
}
|
|
// EVA Fort Park 3
|
Device (FPK3) {
|
Name (_ADR, 0x00000003)
|
}
|
}
|
}
|
}
|
|
// PCI Express Port 2B on PC02
|
Device (BR2B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR21)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH21)
|
}
|
Return (AR21)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// PCI Express Port 2C on PC02
|
Device (BR2C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR22)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH22)
|
}
|
Return (AR22)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// PCI Express Port 2D on PC02
|
Device (BR2D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR23)
|
}
|
If (LEqual(AP02, One)) {
|
Return (AH23)
|
}
|
Return (AR23)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// Uncore 2 M2MEM0 Device
|
Device (M2M0) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// Uncore 2 M2MEM10 Device
|
Device (M2M1) {
|
Name (_ADR, 0x00090000)
|
}
|
|
// Uncore 2 MCMAIN Device
|
Device (MCM0) {
|
Name (_ADR, 0x000A0000)
|
}
|
|
// Uncore 2 MCDECS2 Device
|
Device (MCD0) {
|
Name (_ADR, 0x000B0000)
|
}
|
|
// Uncore 2 MCMAIN Device
|
Device (MCM1) {
|
Name (_ADR, 0x000C0000)
|
}
|
|
// Uncore 2 MCDECS12 Device
|
Device (MCD1) {
|
Name (_ADR, 0x000D0000)
|
}
|
|
// Uncore 2 Unicast MC0 DDRIO0 Device
|
Device (UMC0) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 2 Unicast MC1 DDRIO0 Device
|
Device (UMC1) {
|
Name (_ADR, 0x00170000)
|
}
|
}
|
|
// Socket 0 Root bridge (Stack 3)
|
Device (PC03) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x03)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB03)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR24)
|
}
|
If (LEqual(AP03, One)) {
|
Return (AH24)
|
}
|
Return (AR24)
|
}
|
|
#include "PC03.asi"
|
|
// PCI Express Port 3A on PC03
|
Device (BR3A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR25)
|
}
|
If (LEqual(AP03, One)) {
|
Return (AH25)
|
}
|
Return (AR25)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// PCI Express Port 3B on PC03
|
Device (BR3B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR26)
|
}
|
If (LEqual(AP03, One)) {
|
Return (AH26)
|
}
|
Return (AR26)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// PCI Express Port 3C on PC03
|
Device (BR3C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR27)
|
}
|
If (LEqual(AP03, One)) {
|
Return (AH27)
|
}
|
Return (AR27)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// PCI Express Port 3D on PC03
|
Device (BR3D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR28)
|
}
|
If (LEqual(AP03, One)) {
|
Return (AH28)
|
}
|
Return (AR28)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieNonHpDev.asi"
|
}
|
|
// KTI0
|
Device (KTI0) {
|
Name (_ADR, 0x000E0000)
|
}
|
|
// KTI1
|
Device (KTI1) {
|
Name (_ADR, 0x000F0000)
|
}
|
|
// KTI2
|
Device (KTI2) {
|
Name (_ADR, 0x00100000)
|
}
|
|
// M3K0
|
Device (M3K0) {
|
Name (_ADR, 0x00120000)
|
}
|
|
// M2U0
|
Device (M2U0) {
|
Name (_ADR, 0x00150000)
|
}
|
|
// M2D0
|
Device (M2D0) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// M20
|
Device (M20) {
|
Name (_ADR, 0x00170000)
|
}
|
}
|
|
// Socket 0 Root bridge (Stack 4)
|
Device (PC04) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x04)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB04)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR29)
|
}
|
If (LEqual(AP04, One)) {
|
Return (AH29)
|
}
|
Return (AR29)
|
}
|
|
#include "PC04.asi"
|
|
// PCI Express Port 4 on PC04
|
Device (MCP0) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR2A)
|
}
|
If (LEqual(AP04, One)) {
|
Return (AH2A)
|
}
|
Return (AR2A)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
}
|
}
|
|
// Socket 0 Root bridge (Stack 5)
|
Device (PC05) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x05)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB05)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR2B)
|
}
|
If (LEqual(AP05, One)) {
|
Return (AH2B)
|
}
|
Return (AR2B)
|
}
|
|
#include "PC05.asi"
|
|
// PCI Express Port 5 on PC05
|
Device (MCP1) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR2C)
|
}
|
If (LEqual(AP05, One)) {
|
Return (AH2C)
|
}
|
Return (AR2C)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
}
|
}
|
|
// Socket 1 Root bridge (Stack 0)
|
Device (PC06) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x06)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB06)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR2D)
|
}
|
If (LEqual(AP06, One)) {
|
Return (AH2D)
|
}
|
Return (AR2D)
|
}
|
|
#include "PC06.asi"
|
#include "Sck1Ejd.asi"
|
|
// PCI Express Port 0 on PC06
|
Device (QRP0) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR2E)
|
}
|
If (LEqual(AP06, One)) {
|
Return (AH2E)
|
}
|
Return (AR2E)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// CB3DMA on PC06
|
Device (CB1B) {
|
Name (_ADR, 0x00040001)
|
}
|
|
// CB3DMA on PC06
|
Device (CB1C) {
|
Name (_ADR, 0x00040002)
|
}
|
|
// CB3DMA on PC06
|
Device (CB1D) {
|
Name (_ADR, 0x00040003)
|
}
|
|
// CB3DMA on PC06
|
Device (CB1E) {
|
Name (_ADR, 0x00040004)
|
}
|
|
// CB3DMA on PC06
|
Device (CB1F) {
|
Name (_ADR, 0x00040005)
|
}
|
|
// CB3DMA on PC06
|
Device (CB1G) {
|
Name (_ADR, 0x00040006)
|
}
|
|
// CB3DMA on PC06
|
Device (CB1H) {
|
Name (_ADR, 0x00040007)
|
}
|
|
// IIOMISC on PC01
|
Device (IIM1) {
|
Name (_ADR, 0x00050000)
|
}
|
|
// Uncore 4 UBOX Device
|
Device (UBX1) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// CB3DMA on PC06
|
Device (CB1A) {
|
Name (_ADR, 0x00040000)
|
}
|
}
|
|
// Socket 1 Root bridge (Stack 1)
|
Device (PC07) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x07)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB07)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR2F)
|
}
|
If (LEqual(AP07, One)) {
|
Return (AH2F)
|
}
|
Return (AR2F)
|
}
|
|
#include "PC07.asi"
|
#include "Sck1Ejd.asi"
|
|
// PCI Express Port 1A on PC07
|
Device (QR1A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR30)
|
}
|
If (LEqual(AP07, One)) {
|
Return (AH30)
|
}
|
Return (AR30)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// PCI Express Port 1B on PC07
|
Device (QR1B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR31)
|
}
|
If (LEqual(AP07, One)) {
|
Return (AH31)
|
}
|
Return (AR31)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// PCI Express Port 1C on PC07
|
Device (QR1C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR32)
|
}
|
If (LEqual(AP07, One)) {
|
Return (AH32)
|
}
|
Return (AR32)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// PCI Express Port 1D on PC07
|
Device (QR1D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR33)
|
}
|
If (LEqual(AP07, One)) {
|
Return (AH33)
|
}
|
Return (AR33)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// Uncore 5 CHAUTIL0-7 Device
|
Device (CHB0) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// Uncore 5 CHAUTIL8-15 Device
|
Device (CHB1) {
|
Name (_ADR, 0x00090000)
|
}
|
|
// Uncore 5 CHAUTIL16-23 Device
|
Device (CHB2) {
|
Name (_ADR, 0x000A0000)
|
}
|
|
// Uncore 5 CHAUTIL24-27 Device
|
Device (CHB3) {
|
Name (_ADR, 0x000B0000)
|
}
|
|
// Uncore 5 CHASAD0-7 Device
|
Device (CHB4) {
|
Name (_ADR, 0x000E0000)
|
}
|
|
// Uncore 5 CHASAD8-15 Device
|
Device (CHB5) {
|
Name (_ADR, 0x000F0000)
|
}
|
|
// Uncore 5 CHASAD16-23 Device
|
Device (CHB6) {
|
Name (_ADR, 0x00100000)
|
}
|
|
// Uncore 5 CHASAD24-27 Device
|
Device (CHB7) {
|
Name (_ADR, 0x00110000)
|
}
|
|
// Uncore 5 CMSCHA0-7 Device
|
Device (CMS4) {
|
Name (_ADR, 0x00140000)
|
}
|
|
// Uncore 5 CMS0CHA8-15 Device
|
Device (CMS5) {
|
Name (_ADR, 0x00150000)
|
}
|
|
// Uncore 5 CMS0CHA16-23 Device
|
Device (CMS6) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 5 CMS0CHA24-27 Device
|
Device (CMS7) {
|
Name (_ADR, 0x00170000)
|
}
|
|
// Uncore 5 CHASADALL Device
|
Device (CDL1) {
|
Name (_ADR, 0x001D0000)
|
}
|
|
// Uncore 5 PCUCR Devices
|
Device (PCU1) {
|
Name (_ADR, 0x001E0000)
|
}
|
|
// Uncore 5 VCUCR Device
|
Device (VCU1) {
|
Name (_ADR, 0x001F0000)
|
}
|
}
|
|
// Socket 1 Root bridge (Stack 2)
|
Device (PC08) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x08)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB08)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR34)
|
}
|
If (LEqual(AP08, One)) {
|
Return (AH34)
|
}
|
Return (AR34)
|
}
|
|
#include "PC08.asi"
|
#include "Sck1Ejd.asi"
|
|
// PCI Express Port 2A on PC08
|
Device (QR2A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR35)
|
}
|
If (LEqual(AP08, One)) {
|
Return (AH35)
|
}
|
Return (AR35)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// PCI Express Port 2B on PC08
|
Device (QR2B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR36)
|
}
|
If (LEqual(AP08, One)) {
|
Return (AH36)
|
}
|
Return (AR36)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// PCI Express Port 2C on PC08
|
Device (QR2C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR37)
|
}
|
If (LEqual(AP08, One)) {
|
Return (AH37)
|
}
|
Return (AR37)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// PCI Express Port 2D on PC08
|
Device (QR2D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR38)
|
}
|
If (LEqual(AP08, One)) {
|
Return (AH38)
|
}
|
Return (AR38)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// Uncore 6 M2MEM0 Device
|
Device (M2M2) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// Uncore 6 M2MEM10 Device
|
Device (M2M3) {
|
Name (_ADR, 0x00090000)
|
}
|
|
// Uncore 6 MCMAIN Device
|
Device (MCM2) {
|
Name (_ADR, 0x000A0000)
|
}
|
|
// Uncore 6 MCDECS2 Device
|
Device (MCD2) {
|
Name (_ADR, 0x000B0000)
|
}
|
|
// Uncore 6 MCMAIN Device
|
Device (MCM3) {
|
Name (_ADR, 0x000C0000)
|
}
|
|
// Uncore 6 MCDECS12 Device
|
Device (MCD3) {
|
Name (_ADR, 0x000D0000)
|
}
|
|
// Uncore 6 Unicast MC0 DDRIO0 Device
|
Device (UMC2) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 6 Unicast MC1 DDRIO0 Device
|
Device (UMC3) {
|
Name (_ADR, 0x00170000)
|
}
|
}
|
|
// Socket 1 Root bridge (Stack 3)
|
Device (PC09) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x09)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB09)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR39)
|
}
|
If (LEqual(AP09, One)) {
|
Return (AH39)
|
}
|
Return (AR39)
|
}
|
|
#include "PC09.asi"
|
#include "Sck1Ejd.asi"
|
|
// PCI Express Port 3A on PC09
|
Device (QR3A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR3A)
|
}
|
If (LEqual(AP09, One)) {
|
Return (AH3A)
|
}
|
Return (AR3A)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// PCI Express Port 3B on PC09
|
Device (QR3B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR3B)
|
}
|
If (LEqual(AP09, One)) {
|
Return (AH3B)
|
}
|
Return (AR3B)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// PCI Express Port 3C on PC09
|
Device (QR3C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR3C)
|
}
|
If (LEqual(AP09, One)) {
|
Return (AH3C)
|
}
|
Return (AR3C)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// PCI Express Port 3D on PC09
|
Device (QR3D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR3D)
|
}
|
If (LEqual(AP09, One)) {
|
Return (AH3D)
|
}
|
Return (AR3D)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
|
// Uncore 7 KTI3
|
Device (KTI3) {
|
Name (_ADR, 0x000E0000)
|
}
|
|
// Uncore 7 KTI4
|
Device (KTI4) {
|
Name (_ADR, 0x000F0000)
|
}
|
|
// Uncore 7 KTI5
|
Device (KTI5) {
|
Name (_ADR, 0x00100000)
|
}
|
|
// Uncore 7 M3K1
|
Device (M3K1) {
|
Name (_ADR, 0x00120000)
|
}
|
|
// Uncore 7 M2U1
|
Device (M2U1) {
|
Name (_ADR, 0x00150000)
|
}
|
|
// Uncore 7 M2D1
|
Device (M2D1) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 7 M21
|
Device (M21) {
|
Name (_ADR, 0x00170000)
|
}
|
}
|
|
// Socket 1 Root bridge (Stack 4)
|
Device (PC10) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x0A)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB10)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR3E)
|
}
|
If (LEqual(AP10, One)) {
|
Return (AH3E)
|
}
|
Return (AR3E)
|
}
|
|
#include "PC10.asi"
|
#include "Sck1Ejd.asi"
|
|
// PCI Express Port 13 on PC10
|
Device (MCP2) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR3F)
|
}
|
If (LEqual(AP10, One)) {
|
Return (AH3F)
|
}
|
Return (AR3F)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
}
|
|
// Socket 1 Root bridge (Stack 5)
|
Device (PC11) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x0B)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB11)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR40)
|
}
|
If (LEqual(AP11, One)) {
|
Return (AH40)
|
}
|
Return (AR40)
|
}
|
|
#include "PC11.asi"
|
#include "Sck1Ejd.asi"
|
|
// PCI Express Port 14 on PC11
|
Device (MCP3) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR41)
|
}
|
If (LEqual(AP11, One)) {
|
Return (AH41)
|
}
|
Return (AR41)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC06Ejd.asi"
|
}
|
}
|
|
// Socket 2 Root bridge (Stack 0)
|
Device (PC12) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x0C)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB12)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR42)
|
}
|
If (LEqual(AP12, One)) {
|
Return (AH42)
|
}
|
Return (AR42)
|
}
|
|
#include "PC12.asi"
|
#include "Sck2Ejd.asi"
|
|
// PCI Express Port 0 on PC12
|
Device (RRP0) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR43)
|
}
|
If (LEqual(AP12, One)) {
|
Return (AH43)
|
}
|
Return (AR43)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// CB3DMA on PC12
|
Device (CB2B) {
|
Name (_ADR, 0x00040001)
|
}
|
|
// CB3DMA on PC12
|
Device (CB2C) {
|
Name (_ADR, 0x00040002)
|
}
|
|
// CB3DMA on PC12
|
Device (CB2D) {
|
Name (_ADR, 0x00040003)
|
}
|
|
// CB3DMA on PC12
|
Device (CB2E) {
|
Name (_ADR, 0x00040004)
|
}
|
|
// CB3DMA on PC12
|
Device (CB2F) {
|
Name (_ADR, 0x00040005)
|
}
|
|
// CB3DMA on PC12
|
Device (CB2G) {
|
Name (_ADR, 0x00040006)
|
}
|
|
// CB3DMA on PC12
|
Device (CB2H) {
|
Name (_ADR, 0x00040007)
|
}
|
|
// IIOMISC on PC02
|
Device (IIM2) {
|
Name (_ADR, 0x00050000)
|
}
|
|
// Uncore 8 UBOX Device
|
Device (UBX2) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// CB3DMA on PC12
|
Device (CB2A) {
|
Name (_ADR, 0x00040000)
|
}
|
}
|
|
// Socket 2 Root bridge (Stack 1)
|
Device (PC13) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x0D)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB13)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR44)
|
}
|
If (LEqual(AP13, One)) {
|
Return (AH44)
|
}
|
Return (AR44)
|
}
|
|
#include "PC13.asi"
|
#include "Sck2Ejd.asi"
|
|
// PCI Express Port 1A on PC13
|
Device (RR1A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR45)
|
}
|
If (LEqual(AP13, One)) {
|
Return (AH45)
|
}
|
Return (AR45)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// PCI Express Port 1B on PC13
|
Device (RR1B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR46)
|
}
|
If (LEqual(AP13, One)) {
|
Return (AH46)
|
}
|
Return (AR46)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// PCI Express Port 1C on PC13
|
Device (RR1C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR47)
|
}
|
If (LEqual(AP13, One)) {
|
Return (AH47)
|
}
|
Return (AR47)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// PCI Express Port 1D on PC13
|
Device (RR1D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR48)
|
}
|
If (LEqual(AP13, One)) {
|
Return (AH48)
|
}
|
Return (AR48)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// Uncore 9 CHAUTIL0-7 Device
|
Device (CHC0) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// Uncore 9 CHAUTIL8-15 Device
|
Device (CHC1) {
|
Name (_ADR, 0x00090000)
|
}
|
|
// Uncore 9 CHAUTIL16-23 Device
|
Device (CHC2) {
|
Name (_ADR, 0x000A0000)
|
}
|
|
// Uncore 9 CHAUTIL24-27 Device
|
Device (CHC3) {
|
Name (_ADR, 0x000B0000)
|
}
|
|
// Uncore 9 CHASAD0-7 Device
|
Device (CHC4) {
|
Name (_ADR, 0x000E0000)
|
}
|
|
// Uncore 9 CHASAD8-15 Device
|
Device (CHC5) {
|
Name (_ADR, 0x000F0000)
|
}
|
|
// Uncore 9 CHASAD16-23 Device
|
Device (CHC6) {
|
Name (_ADR, 0x00100000)
|
}
|
|
// Uncore 9 CHASAD24-27 Device
|
Device (CHC7) {
|
Name (_ADR, 0x00110000)
|
}
|
|
// Uncore 9 CMSCHA0-7 Device
|
Device (CMS8) {
|
Name (_ADR, 0x00140000)
|
}
|
|
// Uncore 9 CMS0CHA8-15 Device
|
Device (CMS9) {
|
Name (_ADR, 0x00150000)
|
}
|
|
// Uncore 9 CHASADALL Device
|
Device (CDL2) {
|
Name (_ADR, 0x001D0000)
|
}
|
|
// Uncore 9 PCUCR Devices
|
Device (PCU2) {
|
Name (_ADR, 0x001E0000)
|
}
|
|
// Uncore 9 VCUCR Device
|
Device (VCU2) {
|
Name (_ADR, 0x001F0000)
|
}
|
}
|
|
// Socket 2 Root bridge (Stack 2)
|
Device (PC14) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x0E)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB14)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR49)
|
}
|
If (LEqual(AP14, One)) {
|
Return (AH49)
|
}
|
Return (AR49)
|
}
|
|
#include "PC14.asi"
|
#include "Sck2Ejd.asi"
|
|
// PCI Express Port 2A on PC14
|
Device (RR2A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR4A)
|
}
|
If (LEqual(AP14, One)) {
|
Return (AH4A)
|
}
|
Return (AR4A)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// PCI Express Port 2B on PC14
|
Device (RR2B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR4B)
|
}
|
If (LEqual(AP14, One)) {
|
Return (AH4B)
|
}
|
Return (AR4B)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// PCI Express Port 2C on PC14
|
Device (RR2C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR4C)
|
}
|
If (LEqual(AP14, One)) {
|
Return (AH4C)
|
}
|
Return (AR4C)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// PCI Express Port 2D on PC14
|
Device (RR2D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR4D)
|
}
|
If (LEqual(AP14, One)) {
|
Return (AH4D)
|
}
|
Return (AR4D)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// Uncore 10 M2MEM0 Device
|
Device (M2M4) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// Uncore 10 M2MEM10 Device
|
Device (M2M5) {
|
Name (_ADR, 0x00090000)
|
}
|
|
// Uncore 10 MCMAIN Device
|
Device (MCM4) {
|
Name (_ADR, 0x000A0000)
|
}
|
|
// Uncore 10 MCDECS2 Device
|
Device (MCD4) {
|
Name (_ADR, 0x000B0000)
|
}
|
|
// Uncore 10 MCMAIN Device
|
Device (MCM5) {
|
Name (_ADR, 0x000C0000)
|
}
|
|
// Uncore 10 MCDECS12 Device
|
Device (MCD5) {
|
Name (_ADR, 0x000D0000)
|
}
|
|
// Uncore 10 Unicast MC0 DDRIO0 Device
|
Device (UMC4) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 10 Unicast MC1 DDRIO0 Device
|
Device (UMC5) {
|
Name (_ADR, 0x00170000)
|
}
|
}
|
|
// Socket 2 Root bridge (Stack 3)
|
Device (PC15) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x0F)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB15)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR4E)
|
}
|
If (LEqual(AP15, One)) {
|
Return (AH4E)
|
}
|
Return (AR4E)
|
}
|
|
#include "PC15.asi"
|
#include "Sck2Ejd.asi"
|
|
// PCI Express Port 3A on PC15
|
Device (RR3A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR4F)
|
}
|
If (LEqual(AP15, One)) {
|
Return (AH4F)
|
}
|
Return (AR4F)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// PCI Express Port 3B on PC15
|
Device (RR3B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR50)
|
}
|
If (LEqual(AP15, One)) {
|
Return (AH50)
|
}
|
Return (AR50)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// PCI Express Port 3C on PC15
|
Device (RR3C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR51)
|
}
|
If (LEqual(AP15, One)) {
|
Return (AH51)
|
}
|
Return (AR51)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// PCI Express Port 3D on PC15
|
Device (RR3D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR52)
|
}
|
If (LEqual(AP15, One)) {
|
Return (AH52)
|
}
|
Return (AR52)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
|
// Uncore 11 KTI6
|
Device (KTI6) {
|
Name (_ADR, 0x000E0000)
|
}
|
|
// Uncore 11 KTI7
|
Device (KTI7) {
|
Name (_ADR, 0x000F0000)
|
}
|
|
// Uncore 11 KTI8
|
Device (KTI8) {
|
Name (_ADR, 0x00100000)
|
}
|
|
// Uncore 11 M3K2
|
Device (M3K2) {
|
Name (_ADR, 0x00120000)
|
}
|
|
// Uncore 11 M2U2
|
Device (M2U2) {
|
Name (_ADR, 0x00150000)
|
}
|
|
// Uncore 11 M2D2
|
Device (M2D2) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 11 M22
|
Device (M22) {
|
Name (_ADR, 0x00170000)
|
}
|
}
|
|
// Socket 2 Root bridge (Stack 4)
|
Device (PC16) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x10)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB16)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR53)
|
}
|
If (LEqual(AP16, One)) {
|
Return (AH53)
|
}
|
Return (AR53)
|
}
|
|
#include "PC16.asi"
|
#include "Sck2Ejd.asi"
|
|
// PCI Express Port 4 on PC16
|
Device (MCP4) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR54)
|
}
|
If (LEqual(AP16, One)) {
|
Return (AH54)
|
}
|
Return (AR54)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
}
|
|
// Socket 2 Root bridge (Stack 5)
|
Device (PC17) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x11)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB17)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR55)
|
}
|
If (LEqual(AP17, One)) {
|
Return (AH55)
|
}
|
Return (AR55)
|
}
|
|
#include "PC17.asi"
|
#include "Sck2Ejd.asi"
|
|
// PCI Express Port 5 on PC17
|
Device (MCP5) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR56)
|
}
|
If (LEqual(AP17, One)) {
|
Return (AH56)
|
}
|
Return (AR56)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC12Ejd.asi"
|
}
|
}
|
|
// Socket 3 Root bridge (Stack 0)
|
Device (PC18) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x12)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB18)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR57)
|
}
|
If (LEqual(AP18, One)) {
|
Return (AH57)
|
}
|
Return (AR57)
|
}
|
|
#include "PC18.asi"
|
#include "Sck3Ejd.asi"
|
|
// PCI Express Port 0 on PC18
|
Device (SRP0) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR58)
|
}
|
If (LEqual(AP18, One)) {
|
Return (AH58)
|
}
|
Return (AR58)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// CB3DMA on PC18
|
Device (CB3B) {
|
Name (_ADR, 0x00040001)
|
}
|
|
// CB3DMA on PC18
|
Device (CB3C) {
|
Name (_ADR, 0x00040002)
|
}
|
|
// CB3DMA on PC18
|
Device (CB3D) {
|
Name (_ADR, 0x00040003)
|
}
|
|
// CB3DMA on PC18
|
Device (CB3E) {
|
Name (_ADR, 0x00040004)
|
}
|
|
// CB3DMA on PC18
|
Device (CB3F) {
|
Name (_ADR, 0x00040005)
|
}
|
|
// CB3DMA on PC18
|
Device (CB3G) {
|
Name (_ADR, 0x00040006)
|
}
|
|
// CB3DMA on PC18
|
Device (CB3H) {
|
Name (_ADR, 0x00040007)
|
}
|
|
// IIOMISC on PC03
|
Device (IIM3) {
|
Name (_ADR, 0x00050000)
|
}
|
|
// Uncore 12 UBOX Device
|
Device (UBX3) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// CB3DMA on PC18
|
Device (CB3A) {
|
Name (_ADR, 0x00040000)
|
}
|
}
|
|
// Socket 3 Root bridge (Stack 1)
|
Device (PC19) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x13)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB19)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR59)
|
}
|
If (LEqual(AP19, One)) {
|
Return (AH59)
|
}
|
Return (AR59)
|
}
|
|
#include "PC19.asi"
|
#include "Sck3Ejd.asi"
|
|
// PCI Express Port 1A on PC19
|
Device (SR1A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR5A)
|
}
|
If (LEqual(AP19, One)) {
|
Return (AH5A)
|
}
|
Return (AR5A)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// PCI Express Port 1B on PC19
|
Device (SR1B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR5B)
|
}
|
If (LEqual(AP19, One)) {
|
Return (AH5B)
|
}
|
Return (AR5B)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// PCI Express Port 1C on PC19
|
Device (SR1C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR5C)
|
}
|
If (LEqual(AP19, One)) {
|
Return (AH5C)
|
}
|
Return (AR5C)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// PCI Express Port 1D on PC19
|
Device (SR1D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR5D)
|
}
|
If (LEqual(AP19, One)) {
|
Return (AH5D)
|
}
|
Return (AR5D)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// Uncore 13 CHAUTIL0-7 Device
|
Device (CHD0) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// Uncore 13 CHAUTIL8-15 Device
|
Device (CHD1) {
|
Name (_ADR, 0x00090000)
|
}
|
|
// Uncore 13 CHAUTIL16-23 Device
|
Device (CHD2) {
|
Name (_ADR, 0x000A0000)
|
}
|
|
// Uncore 13 CHAUTIL24-27 Device
|
Device (CHD3) {
|
Name (_ADR, 0x000B0000)
|
}
|
|
// Uncore 13 CHASAD0-7 Device
|
Device (CHD4) {
|
Name (_ADR, 0x000E0000)
|
}
|
|
// Uncore 13 CHASAD8-15 Device
|
Device (CHD5) {
|
Name (_ADR, 0x000F0000)
|
}
|
|
// Uncore 13 CHASAD16-23 Device
|
Device (CHD6) {
|
Name (_ADR, 0x00100000)
|
}
|
|
// Uncore 13 CHASAD24-27 Device
|
Device (CHD7) {
|
Name (_ADR, 0x00110000)
|
}
|
|
// Uncore 13 CMSCHA0-7 Device
|
Device (CM12) {
|
Name (_ADR, 0x00140000)
|
}
|
|
// Uncore 13 CMS0CHA8-15 Device
|
Device (CM13) {
|
Name (_ADR, 0x00150000)
|
}
|
|
// Uncore 13 CMS0CHA16-23 Device
|
Device (CM14) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 13 CMS0CHA24-27 Device
|
Device (CM15) {
|
Name (_ADR, 0x00170000)
|
}
|
|
// Uncore 13 CHASADALL Device
|
Device (CDL3) {
|
Name (_ADR, 0x001D0000)
|
}
|
|
// Uncore 13 PCUCR Devices
|
Device (PCU3) {
|
Name (_ADR, 0x001E0000)
|
}
|
|
// Uncore 13 VCUCR Device
|
Device (VCU3) {
|
Name (_ADR, 0x001F0000)
|
}
|
}
|
|
// Socket 3 Root bridge (Stack 2)
|
Device (PC20) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x14)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB20)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR5E)
|
}
|
If (LEqual(AP20, One)) {
|
Return (AH5E)
|
}
|
Return (AR5E)
|
}
|
|
#include "PC20.asi"
|
#include "Sck3Ejd.asi"
|
|
// PCI Express Port 2A on PC20
|
Device (SR2A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR5F)
|
}
|
If (LEqual(AP20, One)) {
|
Return (AH5F)
|
}
|
Return (AR5F)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// PCI Express Port 2B on PC20
|
Device (SR2B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR60)
|
}
|
If (LEqual(AP20, One)) {
|
Return (AH60)
|
}
|
Return (AR60)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// PCI Express Port 2C on PC20
|
Device (SR2C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR61)
|
}
|
If (LEqual(AP20, One)) {
|
Return (AH61)
|
}
|
Return (AR61)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// PCI Express Port 2D on PC20
|
Device (SR2D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR62)
|
}
|
If (LEqual(AP20, One)) {
|
Return (AH62)
|
}
|
Return (AR62)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// Uncore 14 M2MEM0 Device
|
Device (M2M6) {
|
Name (_ADR, 0x00080000)
|
}
|
|
// Uncore 14 M2MEM10 Device
|
Device (M2M7) {
|
Name (_ADR, 0x00090000)
|
}
|
|
// Uncore 14 MCMAIN Device
|
Device (MCM6) {
|
Name (_ADR, 0x000A0000)
|
}
|
|
// Uncore 14 MCDECS2 Device
|
Device (MCD6) {
|
Name (_ADR, 0x000B0000)
|
}
|
|
// Uncore 14 MCMAIN Device
|
Device (MCM7) {
|
Name (_ADR, 0x000C0000)
|
}
|
|
// Uncore 14 MCDECS12 Device
|
Device (MCD7) {
|
Name (_ADR, 0x000D0000)
|
}
|
|
// Uncore 14 Unicast MC0 DDRIO0 Device
|
Device (UMC6) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 14 Unicast MC1 DDRIO0 Device
|
Device (UMC7) {
|
Name (_ADR, 0x00170000)
|
}
|
}
|
|
// Socket 3 Root bridge (Stack 3)
|
Device (PC21) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x15)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB21)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR63)
|
}
|
If (LEqual(AP21, One)) {
|
Return (AH63)
|
}
|
Return (AR63)
|
}
|
|
#include "PC21.asi"
|
#include "Sck3Ejd.asi"
|
|
// PCI Express Port 3A on PC21
|
Device (SR3A) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR64)
|
}
|
If (LEqual(AP21, One)) {
|
Return (AH64)
|
}
|
Return (AR64)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// PCI Express Port 3B on PC21
|
Device (SR3B) {
|
Name (_ADR, 0x00010000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR65)
|
}
|
If (LEqual(AP21, One)) {
|
Return (AH65)
|
}
|
Return (AR65)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// PCI Express Port 3C on PC21
|
Device (SR3C) {
|
Name (_ADR, 0x00020000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR66)
|
}
|
If (LEqual(AP21, One)) {
|
Return (AH66)
|
}
|
Return (AR66)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// PCI Express Port 3D on PC21
|
Device (SR3D) {
|
Name (_ADR, 0x00030000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR67)
|
}
|
If (LEqual(AP21, One)) {
|
Return (AH67)
|
}
|
Return (AR67)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
|
// Uncore 15 KTI9
|
Device (KTI9) {
|
Name (_ADR, 0x000E0000)
|
}
|
|
// Uncore 15 KT10
|
Device (KT10) {
|
Name (_ADR, 0x000F0000)
|
}
|
|
// Uncore 15 KT11
|
Device (KT11) {
|
Name (_ADR, 0x00100000)
|
}
|
|
// Uncore 15 M3K3
|
Device (M3K3) {
|
Name (_ADR, 0x00120000)
|
}
|
|
// Uncore 15 M2U3
|
Device (M2U3) {
|
Name (_ADR, 0x00150000)
|
}
|
|
// Uncore 15 M2D3
|
Device (M2D3) {
|
Name (_ADR, 0x00160000)
|
}
|
|
// Uncore 15 M23
|
Device (M23) {
|
Name (_ADR, 0x00170000)
|
}
|
}
|
|
// Socket 3 Root bridge (Stack 4)
|
Device (PC22) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x16)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB22)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR68)
|
}
|
If (LEqual(AP22, One)) {
|
Return (AH68)
|
}
|
Return (AR68)
|
}
|
|
#include "PC22.asi"
|
#include "Sck3Ejd.asi"
|
|
// PCI Express Port 4 on PC22
|
Device (MCP6) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR69)
|
}
|
If (LEqual(AP22, One)) {
|
Return (AH69)
|
}
|
Return (AR69)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
}
|
}
|
|
// Socket 3 Root bridge (Stack 5)
|
Device (PC23) {
|
Name (_HID, EISAID("PNP0A08"))
|
Name (_CID, EISAID("PNP0A03"))
|
Name (_UID, 0x17)
|
Method (_BBN, 0, NotSerialized) {
|
return (BB23)
|
}
|
Name (_ADR, 0x00000000)
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR6A)
|
}
|
If (LEqual(AP23, One)) {
|
Return (AH6A)
|
}
|
Return (AR6A)
|
}
|
|
#include "PC23.asi"
|
#include "Sck3Ejd.asi"
|
|
// PCI Express Port 5 on PC23
|
Device (MCP7) {
|
Name (_ADR, 0x00000000)
|
Method (_PRW, 0) {
|
Return (Package (0x02) {0x09, 0x04})
|
}
|
Method (_PRT, 0) {
|
If (LEqual(PICM, Zero)) {
|
Return (PR6B)
|
}
|
If (LEqual(AP23, One)) {
|
Return (AH6B)
|
}
|
Return (AR6B)
|
}
|
|
#include "PcieHp.asi"
|
#include "PcieHpDev.asi"
|
#include "PC18Ejd.asi"
|
|
}
|
}
|
}
|
|
Scope (\_GPE) {
|
// [BR1A]: PCI Express Port 1A on PC01
|
// [BR1B]: PCI Express Port 1B on PC01
|
// [BR1C]: PCI Express Port 1C on PC01
|
// [BR1D]: PCI Express Port 1D on PC01
|
// [BR2A]: PCI Express Port 2A on PC02
|
// [BR2B]: PCI Express Port 2B on PC02
|
// [BR2C]: PCI Express Port 2C on PC02
|
// [BR2D]: PCI Express Port 2D on PC02
|
// [BR3A]: PCI Express Port 3A on PC03
|
// [BR3B]: PCI Express Port 3B on PC03
|
// [BR3C]: PCI Express Port 3C on PC03
|
// [BR3D]: PCI Express Port 3D on PC03
|
// [MCP0]: PCI Express Port 4 on PC04
|
// [MCP1]: PCI Express Port 5 on PC05
|
// [QRP0]: PCI Express Port 0 on PC06
|
// [QR1A]: PCI Express Port 1A on PC07
|
// [QR1B]: PCI Express Port 1B on PC07
|
// [QR1C]: PCI Express Port 1C on PC07
|
// [QR1D]: PCI Express Port 1D on PC07
|
// [QR2A]: PCI Express Port 2A on PC08
|
// [QR2B]: PCI Express Port 2B on PC08
|
// [QR2C]: PCI Express Port 2C on PC08
|
// [QR2D]: PCI Express Port 2D on PC08
|
// [QR3A]: PCI Express Port 3A on PC09
|
// [QR3B]: PCI Express Port 3B on PC09
|
// [QR3C]: PCI Express Port 3C on PC09
|
// [QR3D]: PCI Express Port 3D on PC09
|
// [MCP2]: PCI Express Port 13 on PC10
|
// [MCP3]: PCI Express Port 14 on PC11
|
// [RRP0]: PCI Express Port 0 on PC12
|
// [RR1A]: PCI Express Port 1A on PC13
|
// [RR1B]: PCI Express Port 1B on PC13
|
// [RR1C]: PCI Express Port 1C on PC13
|
// [RR1D]: PCI Express Port 1D on PC13
|
// [RR2A]: PCI Express Port 2A on PC14
|
// [RR2B]: PCI Express Port 2B on PC14
|
// [RR2C]: PCI Express Port 2C on PC14
|
// [RR2D]: PCI Express Port 2D on PC14
|
// [RR3A]: PCI Express Port 3A on PC15
|
// [RR3B]: PCI Express Port 3B on PC15
|
// [RR3C]: PCI Express Port 3C on PC15
|
// [RR3D]: PCI Express Port 3D on PC15
|
// [MCP4]: PCI Express Port 4 on PC16
|
// [MCP5]: PCI Express Port 5 on PC17
|
// [SRP0]: PCI Express Port 0 on PC18
|
// [SR1A]: PCI Express Port 1A on PC19
|
// [SR1B]: PCI Express Port 1B on PC19
|
// [SR1C]: PCI Express Port 1C on PC19
|
// [SR1D]: PCI Express Port 1D on PC19
|
// [SR2A]: PCI Express Port 2A on PC20
|
// [SR2B]: PCI Express Port 2B on PC20
|
// [SR2C]: PCI Express Port 2C on PC20
|
// [SR2D]: PCI Express Port 2D on PC20
|
// [SR3A]: PCI Express Port 3A on PC21
|
// [SR3B]: PCI Express Port 3B on PC21
|
// [SR3C]: PCI Express Port 3C on PC21
|
// [SR3D]: PCI Express Port 3D on PC21
|
// [MCP6]: PCI Express Port 4 on PC22
|
// [MCP7]: PCI Express Port 5 on PC23
|
Method (_L09, 0x0, NotSerialized) {
|
#include "Gpe.asl"
|
Notify (\_SB.PC01.BR1A, 0x02)
|
Notify (\_SB.PC01.BR1B, 0x02)
|
Notify (\_SB.PC01.BR1C, 0x02)
|
Notify (\_SB.PC01.BR1D, 0x02)
|
Notify (\_SB.PC02.BR2A, 0x02)
|
Notify (\_SB.PC02.BR2B, 0x02)
|
Notify (\_SB.PC02.BR2C, 0x02)
|
Notify (\_SB.PC02.BR2D, 0x02)
|
Notify (\_SB.PC03.BR3A, 0x02)
|
Notify (\_SB.PC03.BR3B, 0x02)
|
Notify (\_SB.PC03.BR3C, 0x02)
|
Notify (\_SB.PC03.BR3D, 0x02)
|
Notify (\_SB.PC04.MCP0, 0x02)
|
Notify (\_SB.PC05.MCP1, 0x02)
|
Notify (\_SB.PC06.QRP0, 0x02)
|
Notify (\_SB.PC07.QR1A, 0x02)
|
Notify (\_SB.PC07.QR1B, 0x02)
|
Notify (\_SB.PC07.QR1C, 0x02)
|
Notify (\_SB.PC07.QR1D, 0x02)
|
Notify (\_SB.PC08.QR2A, 0x02)
|
Notify (\_SB.PC08.QR2B, 0x02)
|
Notify (\_SB.PC08.QR2C, 0x02)
|
Notify (\_SB.PC08.QR2D, 0x02)
|
Notify (\_SB.PC09.QR3A, 0x02)
|
Notify (\_SB.PC09.QR3B, 0x02)
|
Notify (\_SB.PC09.QR3C, 0x02)
|
Notify (\_SB.PC09.QR3D, 0x02)
|
Notify (\_SB.PC10.MCP2, 0x02)
|
Notify (\_SB.PC11.MCP3, 0x02)
|
Notify (\_SB.PC12.RRP0, 0x02)
|
Notify (\_SB.PC13.RR1A, 0x02)
|
Notify (\_SB.PC13.RR1B, 0x02)
|
Notify (\_SB.PC13.RR1C, 0x02)
|
Notify (\_SB.PC13.RR1D, 0x02)
|
Notify (\_SB.PC14.RR2A, 0x02)
|
Notify (\_SB.PC14.RR2B, 0x02)
|
Notify (\_SB.PC14.RR2C, 0x02)
|
Notify (\_SB.PC14.RR2D, 0x02)
|
Notify (\_SB.PC15.RR3A, 0x02)
|
Notify (\_SB.PC15.RR3B, 0x02)
|
Notify (\_SB.PC15.RR3C, 0x02)
|
Notify (\_SB.PC15.RR3D, 0x02)
|
Notify (\_SB.PC16.MCP4, 0x02)
|
Notify (\_SB.PC17.MCP5, 0x02)
|
Notify (\_SB.PC18.SRP0, 0x02)
|
Notify (\_SB.PC19.SR1A, 0x02)
|
Notify (\_SB.PC19.SR1B, 0x02)
|
Notify (\_SB.PC19.SR1C, 0x02)
|
Notify (\_SB.PC19.SR1D, 0x02)
|
Notify (\_SB.PC20.SR2A, 0x02)
|
Notify (\_SB.PC20.SR2B, 0x02)
|
Notify (\_SB.PC20.SR2C, 0x02)
|
Notify (\_SB.PC20.SR2D, 0x02)
|
Notify (\_SB.PC21.SR3A, 0x02)
|
Notify (\_SB.PC21.SR3B, 0x02)
|
Notify (\_SB.PC21.SR3C, 0x02)
|
Notify (\_SB.PC21.SR3D, 0x02)
|
Notify (\_SB.PC22.MCP6, 0x02)
|
Notify (\_SB.PC23.MCP7, 0x02)
|
}
|
|
// [EPCU]: EVA PCIe Uplink
|
// [VSP0]: EVA Virtual Switch Port 0
|
// [VSP1]: EVA Virtual Switch Port 1
|
// [VSP2]: EVA Virtual Switch Port 2
|
// [VSP3]: EVA Virtual Switch Port 3
|
Method (_L0B, 0x0, NotSerialized) {
|
Notify (\_SB.PC02.BR2A.EPCU, 0x02)
|
Notify (\_SB.PC02.BR2A.EPCU.VSP0, 0x02)
|
Notify (\_SB.PC02.BR2A.EPCU.VSP1, 0x02)
|
Notify (\_SB.PC02.BR2A.EPCU.VSP2, 0x02)
|
Notify (\_SB.PC02.BR2A.EPCU.VSP3, 0x02)
|
}
|
|
}
|
|
