/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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Name (OPAC, Zero)
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Name (XRST, Zero)
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Name (XUSB, Zero)
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OperationRegion (XPRT, PCI_Config, 0x74, 0x6C)
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Field (XPRT, DWordAcc, NoLock, Preserve)
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{
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, 8,
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PMEE, 1, // PWR_CNTL_STS.PME_En
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, 6,
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PMES, 1, // PWR_CNTL_STS.PME_Sts
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Offset (0x5C),
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PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register.
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PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register.
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PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register.
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PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register
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}
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Method (_PSW,1)
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{
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If (Arg0)
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{
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Store (Ones,PMEE)
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}
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Else
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{
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Store (0,PMEE)
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}
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}
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//
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// Indicate access to OperationRegions is enabled/disabled
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//
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Method (_REG, 2) {
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//
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// If OperationRegion ID = PCI_Config
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//
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If (LEqual (Arg0, 2)) {
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//
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// If access is enabled
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//
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If (LEqual(Arg1, 1)) {
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//
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// Set local flag
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//
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Store (One, OPAC)
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} Else {
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//
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// Clear local flag
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//
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Store (One, OPAC)
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}
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}
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}
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//
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// Initialization for this controller
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//
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Method (_INI, 0) {
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//
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// If access to OperationRegion is enabled
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//
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If (LEqual (OPAC, One)) {
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Store (1, PMES) // clear PME status
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Store (0, PMEE) // clear PME enable
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}
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}
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//
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// _OSC for xHCI
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// This method enables XHCI controller if available.
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//
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// Arguments:
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// Arg0 (Integer): Revision ID - should be set to 1
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//
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// Arg1 (Integer): Count of DWords in Arg3
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//
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// Arg2 (Buffer) : Capabilities Buffer
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// DWORD #0 (Status/Error):
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// Bit 0 - Query Support Flag
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// Bit 1 - Always clear(0)
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// Bit 2 - Always clear(0)
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// Bit 3 - Always clear(0)
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//
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// All others - reserved
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//
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// DWORD #1 (Supported):
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// Bit 0 - 1: Switch to xHCI
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//
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// All others - reserved
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//
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// DWORD #2 (Controlled):
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// Bit 0 - 1: Clear Smart Auto state (disable xHCI)
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//
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// All others - reserved
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//
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// Returns:
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// Capabilities Buffer:
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// DWORD #0 (Status):
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// Bit 0 - Reserved (not used)
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//
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// Bit 1 - _OSC failure. Platform Firmware was unable to process the request or query.
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// Capabilities bits may have been masked.
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//
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// Bit 2 - Unrecognized UUID. This bit is set to indicate that the platform firmware
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// does not recognize the UUID passed in _OSC Arg0.
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// Capabilities bits are preserved.
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//
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// Bit 3 - Unrecognized Revision. This bit is set to indicate that the platform firmware
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// does not recognize the Revision ID passed in via Arg1.
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// Capabilities bits beyond those comprehended by the firmware will be masked.
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//
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// Bit 4 - Capabilities Masked. This bit is set to indicate
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// that capabilities bits set by driver software
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// have been cleared by platform firmware.
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//
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// Bit 5 - 0: EHCI controller exposed to OS
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// 1: xHCI controller exposed to OS
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//
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// All others - reserved (return 0)
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//
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// DWORD #1 (Supported):
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// Bit 0 - 0: EHCI supported
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// 1: xHCI supported
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//
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// All others - reserved
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//
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// DWORD #2 (Controlled):
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//
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// All bits - reserved
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//
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Method (POSC, 3) {
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Store (0x81, IO80)
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//
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// Create DWord fields from the Capabilities Buffer
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//
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CreateDWordField (Arg2, 0, CDW1) // CDW1 = DWORD that starts at offset 0 of Arg2
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CreateDWordField (Arg2, 4, CDW2) // CDW2 = DWORD that starts at offset 4 of Arg2
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CreateDWordField (Arg2, 8, CDW3) // CDW3 = DWORD that starts at offset 8 of Arg2
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//
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// Are we running a version of Windows that runs the Intel xHCI driver?
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// i.e. Windows Server 2008 through Windows Server 2008 R2 & Windows 7
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//
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If (LAnd (LGreaterEqual (\_SB.OSYS, 9), LLessEqual (\_SB.OSYS, 12))) {
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//
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// Running Windows
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// Check revision is >= 2
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//
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If (LLess (Arg0, 2)) {
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//
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// Set unknown revision bit
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//
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Or (CDW1, 8, CDW1)
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Store (0x82, IO80)
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}
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} Else {
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//
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// If the Intel xHCI driver not calling,
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// then it must be SVOS
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If (LNotEqual (Arg0, 1)) {
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//
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// Set unknown revision bit
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//
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Or (CDW1, 8, CDW1)
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Store (0x82, IO80)
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}
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}
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//
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// Set failure if xHCI is disabled by BIOS
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//
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If (LEqual (XHMD, 0)) {
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Or (CDW1, 2, CDW1)
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Store (0x83, IO80)
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}
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//
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// If no error bits set
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//
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If (LEqual (And (CDW1, 0xE), 0)) {
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//
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// If not just querying support
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//
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If (LNot (And (CDW1, 1))) {
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//
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// If uninstaller calling
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// to switch back to EHCI
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//
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If (And (CDW3, 1)) {
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//
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// Switch to EHCI
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//
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ESEL()
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Store (0x85, IO80)
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//
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// And clear ACPINVS variable
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// that is a copy of USB3.0 setup option
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// so that we will not re-enable xHCI until
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// the next reboot
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//
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Store (0, XHMD)
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}
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//
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// Uninstaller not calling,
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// OS wants to enable xHCI?
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//
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If (And (CDW2, 1)) {
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//
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// Switch to xHCI
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//
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XSEL(0)
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Store (0x84, IO80)
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} Else {
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//
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// Switch to EHCI
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//
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ESEL()
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Store (0x85, IO80)
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}
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}
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}
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Return(Arg2)
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}
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//
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// Put all ports in XHCI mode
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//
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Method (XSEL, 1, Serialized) {
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//
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// If xHCI in auto or smart auto mode
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// or Arg0 == 1
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//
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If ( LOr (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3)), Arg0) ) {
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//
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// If xHCI in smart auto mode
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//
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If (LEqual (XHMD, 3)) {
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//
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// Set B0:D31:F0 ACh[16] to indicate OS has routed ports to xHCI controller
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//
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Store (1, \_SB.PC00.LPC0.XSMB)
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}
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//
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// Set flags so on Sx resume, we'll know OS has previously
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// routed ports to xHCI
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//
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Store (1, XUSB)
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Store (1, XRST) // Backup XUSB, cause it might lost in iRST G3 or DeepSx
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//
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// Enable selected SS ports, route corresponding HS ports to xHCI
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//
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Store (0, Local0)
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And (PR3, 0xFFFFFFC0, Local0)
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Or (Local0, PR3M, PR3)
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Store (0, Local0)
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And (PR2, 0xFFFF8000, Local0)
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Or (Local0, PR2M, PR2)
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}
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}
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//
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// Put all ports in EHCI mode
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//
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Method (ESEL, 0, Serialized) {
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//
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// xHCI in auto or smart auto mode
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//
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If (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3))) {
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//
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// Disable all SS ports, route all HS ports to EHCI
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//
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And (PR3, 0xFFFFFFC0, PR3)
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And (PR2, 0xFFFF8000, PR2)
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//
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// Mark as not routed.
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//
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Store (0, XUSB)
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Store (0, XRST)
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}
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}
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Method (XWAK, 0, Serialized) {
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//
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// If ports were routed to xHCI before sleep
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//
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If (LOr (LEqual (XUSB, 1), LEqual (XRST, 1))) {
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//
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// Restore back to xHCI, ignore XHMD
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//
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XSEL(1)
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//
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// And tell OS to re-enumerate xHCI
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//
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Notify (\_SB.PC00.XHCI, 0x00)
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}
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}
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//
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// Report what D state the controller is in
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// when the system changes to S3 and S4
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//
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Method(_S3D, 0, NotSerialized) {
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Return(2)
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}
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Method(_S4D, 0, NotSerialized) {
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Return(2)
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}
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