/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2021, American Megatrends International LLC.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// Statements that include other files
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//
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//
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// Statements that include other header files
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//
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/PcdLib.h>
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#include <Guid/MemoryMapData.h>
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#include <Guid/GlobalVariable.h>
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#include <IndustryStandard/HighPrecisionEventTimerTable.h>
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#include <Platform.h>
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#include <Acpi/GlobalNvsAreaDef.h>
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#include <Protocol/IioUds.h>
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#include <Protocol/CpuIo2.h>
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#include <Protocol/SerialIo.h>
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#include <Protocol/DevicePath.h>
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#include <IndustryStandard/Acpi.h>
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#include <IndustryStandard/HighPrecisionEventTimerTable.h>
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#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
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#include <IndustryStandard/AcpiAml.h>
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#include <Guid/SocketMpLinkVariable.h>
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#include <Guid/SocketIioVariable.h>
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#include <Guid/SocketPowermanagementVariable.h>
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#include <Guid/SocketCommonRcVariable.h>
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#include "Register/PchRegsUsb.h"
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#include <PiDxe.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiRuntimeServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <IndustryStandard/Acpi.h>
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#include <Protocol/MpService.h>
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#include <Protocol/AcpiSystemDescriptionTable.h>
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extern BOOLEAN mCpuOrderSorted;
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typedef struct {
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char *Pathname; /* Full pathname (from root) to the object */
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unsigned short ParentOpcode; /* AML opcode for the parent object */
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unsigned long NamesegOffset; /* Offset of last nameseg in the parent namepath */
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unsigned char Opcode; /* AML opcode for the data */
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unsigned long Offset; /* Offset for the data */
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unsigned long long Value; /* Original value of the data (as applicable) */
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} AML_OFFSET_TABLE_ENTRY;
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extern AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer;
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extern AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[];
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#define AML_NAME_OP 0x08
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#define AML_NAME_PREFIX_SIZE 0x06
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#define AML_NAME_DWORD_SIZE 0x0C
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#define MEM_ADDR_SHFT_VAL 26 // For 64 MB granularity
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#pragma pack(1)
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typedef struct {
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UINT8 DescriptorType;
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UINT16 ResourceLength;
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UINT8 ResourceType;
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UINT8 Flags;
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UINT8 SpecificFlags;
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UINT64 Granularity;
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UINT64 Minimum;
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UINT64 Maximum;
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UINT64 TranslationOffset;
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UINT64 AddressLength;
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} AML_RESOURCE_ADDRESS64;
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typedef struct {
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UINT8 DescriptorType;
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UINT16 ResourceLength;
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UINT8 ResourceType;
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UINT8 Flags;
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UINT8 SpecificFlags;
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UINT32 Granularity;
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UINT32 Minimum;
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UINT32 Maximum;
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UINT32 TranslationOffset;
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UINT32 AddressLength;
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} AML_RESOURCE_ADDRESS32;
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typedef struct {
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UINT8 DescriptorType;
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UINT16 ResourceLength;
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UINT8 ResourceType;
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UINT8 Flags;
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UINT8 SpecificFlags;
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UINT16 Granularity;
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UINT16 Minimum;
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UINT16 Maximum;
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UINT16 TranslationOffset;
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UINT16 AddressLength;
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} AML_RESOURCE_ADDRESS16;
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#pragma pack()
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#define PCIE_PORT_4_DEV 0x00
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#define PCIE_PORT_5_DEV 0x00
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#define PORTS_PER_SOCKET 0x0F
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#define PCIE_PORT_ALL_FUNC 0x00
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typedef struct _PCIE_PORT_INFO {
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UINT8 Device;
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UINT8 Stack;
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} PCIE_PORT_INFO;
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#pragma optimize("",off)
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extern BIOS_ACPI_PARAM *mAcpiParameter;
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extern struct SystemMemoryMapHob *mSystemMemoryMap;
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extern EFI_IIO_UDS_PROTOCOL *mIioUds;
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extern SOCKET_MP_LINK_CONFIGURATION mSocketMpLinkConfiguration;
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extern SOCKET_IIO_CONFIGURATION mSocketIioConfiguration;
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extern SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfiguration;
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extern UINT32 mNumOfBitShift;
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AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer = DSDT_PLATWFP__OffsetTable;
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/**
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Update the DSDT table
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@param *TableHeader - The table to be set
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@retval EFI_SUCCESS - DSDT updated
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@retval EFI_INVALID_PARAMETER - DSDT not updated
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**/
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EFI_STATUS
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PatchDsdtTable (
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IN OUT EFI_ACPI_COMMON_HEADER *Table
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)
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{
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PCIE_PORT_INFO PCIEPortDefaults[] = {
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// DMI/PCIE 0
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{ PCIE_PORT_0_DEV, IIO_CSTACK },
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//IOU0
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{ PCIE_PORT_1A_DEV, IIO_PSTACK0 },
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{ PCIE_PORT_1B_DEV, IIO_PSTACK0 },
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{ PCIE_PORT_1C_DEV, IIO_PSTACK0 },
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{ PCIE_PORT_1D_DEV, IIO_PSTACK0 },
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//IOU1
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{ PCIE_PORT_2A_DEV, IIO_PSTACK1 },
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{ PCIE_PORT_2B_DEV, IIO_PSTACK1 },
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{ PCIE_PORT_2C_DEV, IIO_PSTACK1 },
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{ PCIE_PORT_2D_DEV, IIO_PSTACK1 },
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//IOU2
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{ PCIE_PORT_3A_DEV, IIO_PSTACK2 },
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{ PCIE_PORT_3B_DEV, IIO_PSTACK2 },
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{ PCIE_PORT_3C_DEV, IIO_PSTACK2 },
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{ PCIE_PORT_3D_DEV, IIO_PSTACK2 },
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//MCP0 and MCP1
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{ PCIE_PORT_4_DEV, IIO_PSTACK3 },
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{ PCIE_PORT_5_DEV, IIO_PSTACK4 }
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};
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EFI_STATUS Status;
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UINT8 *DsdtPointer;
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UINT32 *Signature;
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UINT32 Fixes, NodeIndex;
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UINT8 Counter;
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UINT16 i; // DSDT_PLATEXRP_OffsetTable LUT entries extends beyond 256!
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UINT64 MemoryBaseLimit = 0;
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UINT64 PciHGPEAddr = 0;
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UINT64 BusDevFunc = 0;
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UINT64 PcieHpBus = 0;
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UINT64 PcieHpDev = 0;
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UINT64 PcieHpFunc= 0;
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UINT8 PortCount = 0;
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UINT8 StackNumBus = 0;
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UINT8 StackNumIo = 0;
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UINT8 StackNumMem32 = 0;
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UINT8 StackNumMem64 = 0;
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UINT8 StackNumVgaIo0 = 1; // Start looking for Stack 1
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UINT8 StackNumVgaIo1 = 1; // Start looking for Stack 1
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UINT8 StackNumVgaMmioL = 0;
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UINT8 Stack = 0;
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UINT8 CurrSkt = 0, CurrStack = 0;
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UINT64 IioBusIndex = 0;
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UINT8 BusBase = 0, BusLimit = 0;
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UINT16 IoBase = 0, IoLimit = 0;
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UINT32 MemBase32 = 0, MemLimit32 = 0;
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UINT64 MemBase64 = 0, MemLimit64 = 0;
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AML_RESOURCE_ADDRESS16 *AmlResourceAddress16Pointer;
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AML_RESOURCE_ADDRESS32 *AmlResourceAddress32Pointer;
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AML_RESOURCE_ADDRESS64 *AmlResourceAddress64Pointer;
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EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
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Status = EFI_SUCCESS;
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TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *)Table;
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if (mAmlOffsetTablePointer == NULL) return EFI_INVALID_PARAMETER;
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mAcpiParameter->MemoryBoardBitMask = 0;
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for(Counter = 0; Counter < mSystemMemoryMap->numberEntries; Counter++) {
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NodeIndex = mSystemMemoryMap->Element[Counter].NodeId;
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if((mAcpiParameter->MemoryBoardBitMask) & (1 << NodeIndex)){
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MemoryBaseLimit = mAcpiParameter->MemoryBoardRange[NodeIndex] + LShiftU64(mSystemMemoryMap->Element[Counter].ElementSize, MEM_ADDR_SHFT_VAL);
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mAcpiParameter->MemoryBoardRange[NodeIndex] = MemoryBaseLimit;
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} else {
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mAcpiParameter->MemoryBoardBitMask |= 1 << NodeIndex;
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MemoryBaseLimit = LShiftU64(mSystemMemoryMap->Element[Counter].BaseAddress, 30);
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mAcpiParameter->MemoryBoardBase[NodeIndex] = MemoryBaseLimit;
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MemoryBaseLimit = LShiftU64((mSystemMemoryMap->Element[Counter].BaseAddress + mSystemMemoryMap->Element[Counter].ElementSize), MEM_ADDR_SHFT_VAL);
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mAcpiParameter->MemoryBoardRange[NodeIndex] = MemoryBaseLimit;
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}
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}
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//
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// Mark all spare memory controllers as 1 in MemSpareMask bitmap.
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//
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mAcpiParameter->MemSpareMask = ~mAcpiParameter->MemoryBoardBitMask;
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mAcpiParameter->IioPresentBitMask = 0;
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mAcpiParameter->SocketBitMask = 0;
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for (Counter = 0; Counter < MAX_SOCKET; Counter++) {
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if (!mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Counter].Valid) continue;
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mAcpiParameter->SocketBitMask |= 1 << Counter;
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mAcpiParameter->IioPresentBitMask |= LShiftU64(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Counter].stackPresentBitmap, (Counter * 8));
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for (Stack = 0; Stack < MAX_IIO_STACK; Stack++) {
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mAcpiParameter->BusBase[Counter * MAX_IIO_STACK + Stack] = mIioUds->IioUdsPtr->PlatformData.IIO_resource[Counter].StackRes[Stack].BusBase;
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}
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}
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PciHGPEAddr = mIioUds->IioUdsPtr->PlatformData.PciExpressBase + 0x188;
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BusDevFunc = 0x00;
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PcieHpBus = 0;
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PcieHpDev = 0;
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PcieHpFunc = 0;
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Fixes = 0;
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//
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// Loop through the AML looking for values that we must fix up.
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//
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for (i = 0; mAmlOffsetTablePointer[i].Pathname != 0; i++) {
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//
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// Point to offset in DSDT for current item in AmlOffsetTable.
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//
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DsdtPointer = (UINT8 *) (TableHeader) + mAmlOffsetTablePointer[i].Offset;
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if (mAmlOffsetTablePointer[i].Opcode == AML_DWORD_PREFIX) {
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//
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// If Opcode is 0x0C, then operator is Name() or OperationRegion().
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// (TableHeader + AmlOffsetTable.Offset) is at offset for value to change.
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//
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// The assert below confirms that AML structure matches the offsets table.
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// If not then patching the AML would just corrupt it and result in OS failure.
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// If you encounter this assert something went wrong in *.offset.h files
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// generation. Remove the files and rebuild.
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//
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ASSERT(DsdtPointer[-1] == mAmlOffsetTablePointer[i].Opcode);
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//
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// AmlOffsetTable.Value has FIX tag, so check that to decide what to modify.
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//
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Signature = (UINT32 *) (&mAmlOffsetTablePointer[i].Value);
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switch (*Signature) {
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//
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// PSYS - "FIX0" OperationRegion() in Acpi\AcpiTables\Dsdt\CommonPlatform.asi
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//
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case (SIGNATURE_32 ('F', 'I', 'X', '0')):
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DEBUG ((DEBUG_INFO, "FIX0 - 0x%x\n", mAcpiParameter));
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* (UINT32 *) DsdtPointer = (UINT32) (UINTN) mAcpiParameter;
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Fixes++;
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break;
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//
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// "FIX8" OperationRegion() in Acpi\AcpiTables\Dsdt\PcieHp.asi
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//
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case (SIGNATURE_32 ('F', 'I', 'X', '8')):
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Stack = PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Stack;
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PcieHpBus = mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioBusIndex].StackRes[Stack].BusBase;
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PcieHpDev = PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Device;
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PcieHpFunc = PCIE_PORT_ALL_FUNC;
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//DEBUG((DEBUG_ERROR,"IioBus = %x, hpDev = %x, HpFunc= %x\n",IioBusIndex, PcieHpDev,PcieHpFunc));
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PciHGPEAddr &= ~(0xFFFF000); // clear bus device func numbers
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BusDevFunc = (PcieHpBus << 8) | (PcieHpDev << 3) | PcieHpFunc;
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* (UINT32 *) DsdtPointer = (UINT32) (UINTN) (PciHGPEAddr + (BusDevFunc << 12));
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//DEBUG((DEBUG_ERROR,", BusDevFunc= %x, PortCount = %x\n",BusDevFunc, PortCount));
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PortCount++;
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Fixes++;
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break;
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default:
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break;
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}
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} else if (mAmlOffsetTablePointer[i].Opcode == AML_INDEX_OP) {
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//
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// If Opcode is 0x88, then operator is WORDBusNumber() or WORDIO().
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// (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS16 to change values.
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//
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AmlResourceAddress16Pointer = (AML_RESOURCE_ADDRESS16 *) (DsdtPointer);
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//
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// The assert below confirms that AML structure matches the offsets table.
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// If not then patching the AML would just corrupt it and result in OS failure.
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// If you encounter this assert something went wrong in *.offset.h files
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// generation. Remove the files and rebuild.
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//
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ASSERT(AmlResourceAddress16Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode);
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//
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// Last 4 chars of AmlOffsetTable.Pathname has FIX tag.
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//
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Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4);
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switch (*Signature) {
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//
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// "FIX1" BUS resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
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//
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case (SIGNATURE_32 ('F', 'I', 'X', '1')):
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CurrSkt = StackNumBus / MAX_IIO_STACK;
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CurrStack = StackNumBus % MAX_IIO_STACK;
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BusBase = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].BusBase;
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BusLimit = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].BusLimit;
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AmlResourceAddress16Pointer->Granularity = 0;
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if (BusLimit > BusBase) {
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AmlResourceAddress16Pointer->Minimum = (UINT16) BusBase;
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AmlResourceAddress16Pointer->Maximum = (UINT16) BusLimit;
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AmlResourceAddress16Pointer->AddressLength = (UINT16) (BusLimit - BusBase + 1);
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}
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//DEBUG((DEBUG_ERROR,", FIX1 BusBase = 0x%x, BusLimit = 0x%x\n",BusBase, BusLimit));
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StackNumBus++;
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Fixes++;
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break;
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//
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// "FIX2" IO resource for for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
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//
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case (SIGNATURE_32 ('F', 'I', 'X', '2')):
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AmlResourceAddress16Pointer->Granularity = 0;
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CurrSkt = StackNumIo / MAX_IIO_STACK;
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CurrStack = StackNumIo % MAX_IIO_STACK;
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IoBase = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceIoBase;
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IoLimit = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceIoLimit;
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if (IoLimit > IoBase) {
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AmlResourceAddress16Pointer->Minimum = (UINT16) IoBase;
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AmlResourceAddress16Pointer->Maximum = (UINT16) IoLimit;
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AmlResourceAddress16Pointer->AddressLength = (UINT16) (IoLimit - IoBase + 1);
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}
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//DEBUG((DEBUG_ERROR,", FIX2 IoBase = 0x%x, IoLimit = 0x%x\n",IoBase, IoLimit));
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StackNumIo++;
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Fixes++;
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break;
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//
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// "FIX6" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi
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//
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case (SIGNATURE_32 ('F', 'I', 'X', '6')):
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AmlResourceAddress16Pointer->Granularity = 0;
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CurrSkt = StackNumVgaIo0 / MAX_IIO_STACK;
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CurrStack = StackNumVgaIo0 % MAX_IIO_STACK;
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if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) &&
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(mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)){
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AmlResourceAddress16Pointer->Minimum = (UINT16) 0x03b0;
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AmlResourceAddress16Pointer->Maximum = (UINT16) 0x03bb;
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AmlResourceAddress16Pointer->AddressLength = (UINT16) 0x000C;
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}
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StackNumVgaIo0++;
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Fixes++;
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break;
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//
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// "FIX7" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi
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//
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case (SIGNATURE_32 ('F', 'I', 'X', '7')):
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AmlResourceAddress16Pointer->Granularity = 0;
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CurrSkt = StackNumVgaIo1 / MAX_IIO_STACK;
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CurrStack = StackNumVgaIo1 % MAX_IIO_STACK;
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if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) &&
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(mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)) {
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AmlResourceAddress16Pointer->Minimum = (UINT16) 0x03c0;
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AmlResourceAddress16Pointer->Maximum = (UINT16) 0x03df;
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AmlResourceAddress16Pointer->AddressLength = (UINT16) 0x0020;
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}
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StackNumVgaIo1++;
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Fixes++;
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break;
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default:
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break;
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}
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} else if (mAmlOffsetTablePointer[i].Opcode == AML_SIZE_OF_OP) {
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//
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// If Opcode is 0x87, then operator is DWORDMemory().
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// (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS32 to change values.
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//
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AmlResourceAddress32Pointer = (AML_RESOURCE_ADDRESS32 *) (DsdtPointer);
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//
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// The assert below confirms that AML structure matches the offsets table.
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// If not then patching the AML would just corrupt it and result in OS failure.
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// If you encounter this assert something went wrong in *.offset.h files
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// generation. Remove the files and rebuild.
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//
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ASSERT(AmlResourceAddress32Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode);
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//
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// Last 4 chars of AmlOffsetTable.Pathname has FIX tag.
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//
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Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4);
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switch (*Signature) {
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//
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// "FIX3" PCI32 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
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//
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case (SIGNATURE_32 ('F', 'I', 'X', '3')):
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AmlResourceAddress32Pointer->Granularity = 0;
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CurrSkt = StackNumMem32 / MAX_IIO_STACK;
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CurrStack = StackNumMem32 % MAX_IIO_STACK;
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MemBase32 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem32Base;
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MemLimit32 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem32Limit;
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if (MemLimit32 > MemBase32) {
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AmlResourceAddress32Pointer->Minimum = (UINT32) MemBase32;
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AmlResourceAddress32Pointer->Maximum = (UINT32) MemLimit32;
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AmlResourceAddress32Pointer->AddressLength = (UINT32) (MemLimit32 - MemBase32 + 1);
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}
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//DEBUG((DEBUG_ERROR,", FIX3 MemBase32 = 0x%08x, MemLimit32 = 0x%08x\n",MemBase32, MemLimit32));
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StackNumMem32++;
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Fixes++;
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break;
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//
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// "FIX5" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi
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//
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case (SIGNATURE_32 ('F', 'I', 'X', '5')):
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AmlResourceAddress32Pointer->Granularity = 0;
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CurrSkt = StackNumVgaMmioL / MAX_IIO_STACK;
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CurrStack = StackNumVgaMmioL % MAX_IIO_STACK;
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if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) &&
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(mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)) {
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AmlResourceAddress32Pointer->Minimum = 0x000a0000;
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AmlResourceAddress32Pointer->Maximum = 0x000bffff;
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AmlResourceAddress32Pointer->AddressLength = 0x00020000;
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}
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StackNumVgaMmioL++;
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Fixes++;
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break;
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default:
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break;
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}
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} else if (mAmlOffsetTablePointer[i].Opcode == AML_CREATE_DWORD_FIELD_OP) {
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//
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// If Opcode is 0x8A, then operator is QWORDMemory().
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// (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS64 to change values.
|
//
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AmlResourceAddress64Pointer = (AML_RESOURCE_ADDRESS64 *) (DsdtPointer);
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//
|
// The assert below confirms that AML structure matches the offsets table.
|
// If not then patching the AML would just corrupt it and result in OS failure.
|
// If you encounter this assert something went wrong in *.offset.h files
|
// generation. Remove the files and rebuild.
|
//
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ASSERT(AmlResourceAddress64Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode);
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//
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// Last 4 chars of AmlOffsetTable.Pathname has FIX tag.
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//
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Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4);
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switch (*Signature) {
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//
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// "FIX4" PCI64 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
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//
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case (SIGNATURE_32 ('F', 'I', 'X', '4')):
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DEBUG((DEBUG_ERROR,"Pci64BitResourceAllocation = 0x%x\n",mSocketIioConfiguration.Pci64BitResourceAllocation));
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if (mSocketIioConfiguration.Pci64BitResourceAllocation) {
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AmlResourceAddress64Pointer->Granularity = 0;
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CurrSkt = StackNumMem64 / MAX_IIO_STACK;
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CurrStack = StackNumMem64 % MAX_IIO_STACK;
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MemBase64 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem64Base;
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MemLimit64 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem64Limit;
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if (MemLimit64 > MemBase64) {
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AmlResourceAddress64Pointer->Minimum = (UINT64) MemBase64;
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AmlResourceAddress64Pointer->Maximum = (UINT64) MemLimit64;
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AmlResourceAddress64Pointer->AddressLength = (UINT64) (MemLimit64 - MemBase64 + 1);
|
}
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DEBUG((DEBUG_ERROR,", FIX4 MemBase64 = 0x%x, MemLimit64 = 0x%x\n",MemBase64, MemLimit64));
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StackNumMem64++;
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Fixes++;
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}
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break;
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default:
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break;
|
}
|
}
|
}
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|
//return Status;
|
return EFI_SUCCESS;
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}
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