/** @file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <PiSmm.h>
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#include <Library/TestPointCheckLib.h>
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#include <Library/TestPointLib.h>
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#include <Library/DebugLib.h>
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#include <Register/Cpuid.h>
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#include <Register/Msr.h>
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//
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// Machine Specific Registers (MSRs)
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//
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#define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE
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#define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2
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#define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3
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#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0
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#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
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BOOLEAN mSmrrSupported = FALSE;
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//
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// Set default value to assume IA-32 Architectural MSRs are used
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//
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UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
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UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;
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EFI_STATUS
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TestPointCheckSmrr (
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VOID
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)
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{
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UINT64 SmrrBase;
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UINT64 SmrrMask;
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UINT64 Length;
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UINT32 RegEax;
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UINT32 RegEdx;
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UINTN FamilyId;
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UINTN ModelId;
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BOOLEAN Result;
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DEBUG ((DEBUG_INFO, "==== TestPointCheckSmrr - Enter\n"));
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//
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// Retrieve CPU Family and Model
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//
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AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
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FamilyId = (RegEax >> 8) & 0xf;
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ModelId = (RegEax >> 4) & 0xf;
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if (FamilyId == 0x06 || FamilyId == 0x0f) {
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ModelId = ModelId | ((RegEax >> 12) & 0xf0);
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}
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//
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// Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
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//
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if ((RegEdx & BIT12) != 0) {
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//
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// Check MTRR_CAP MSR bit 11 for SMRR support
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//
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if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {
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mSmrrSupported = TRUE;
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}
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
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//
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// If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
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// SMRR Physical Base and SMM Physical Mask MSRs are not available.
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//
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if (FamilyId == 0x06) {
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if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {
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mSmrrSupported = FALSE;
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}
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
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//
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// If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
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// Processor Family MSRs
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//
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if (FamilyId == 0x06) {
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if (ModelId == 0x17 || ModelId == 0x0f) {
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mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
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mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
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}
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}
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SmrrMask = 0;
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if (mSmrrSupported) {
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SmrrBase = AsmReadMsr64 (mSmrrPhysBaseMsr);
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SmrrMask = AsmReadMsr64 (mSmrrPhysMaskMsr);
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DEBUG ((DEBUG_INFO, "SMRR : Base=%016lx Make=%016lx\n", SmrrBase, SmrrMask));
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}
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DEBUG ((DEBUG_INFO, "==== TestPointCheckSmrr - Exit\n"));
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Result = TRUE;
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if (!mSmrrSupported) {
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Result = FALSE;
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DEBUG ((DEBUG_ERROR, "Smrr is not supported\n"));
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} else {
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Length = SmrrMask & ~0xFFFull;
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Length = ~Length + 1;
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Length = Length & 0xFFFFF000;
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if (Length != GetPowerOfTwo64 (Length)) {
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Result = FALSE;
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DEBUG ((DEBUG_ERROR, "Smrr is not aligned\n"));
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}
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}
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if (!Result) {
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TestPointLibAppendErrorString (
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PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV,
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NULL,
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TEST_POINT_BYTE6_SMM_END_OF_DXE_SMRR_FUNCTIONAL_ERROR_CODE \
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TEST_POINT_SMM_END_OF_DXE \
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TEST_POINT_BYTE6_SMM_END_OF_DXE_SMRR_FUNCTIONAL_ERROR_STRING
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);
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return EFI_INVALID_PARAMETER;
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}
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return EFI_SUCCESS;
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}
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