/** @file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <PiDxe.h>
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#include <Library/TestPointCheckLib.h>
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#include <Library/TestPointLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/PciIo.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PciSegmentInfoLib.h>
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#include <IndustryStandard/Pci.h>
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#pragma pack(1)
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//
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// Data region after PCI configuration header(for cardbus bridge)
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//
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typedef struct {
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UINT16 SubVendorId; // Subsystem Vendor ID
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UINT16 SubSystemId; // Subsystem ID
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UINT32 LegacyBase; // Optional 16-Bit PC Card Legacy
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// Mode Base Address
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//
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UINT32 Data[46];
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} PCI_CARDBUS_DATA;
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typedef union {
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PCI_DEVICE_HEADER_TYPE_REGION Device;
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PCI_BRIDGE_CONTROL_REGISTER Bridge;
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PCI_CARDBUS_CONTROL_REGISTER CardBus;
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} NON_COMMON_UNION;
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typedef struct {
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PCI_DEVICE_INDEPENDENT_REGION Common;
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NON_COMMON_UNION NonCommon;
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UINT32 Data[48];
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} PCI_CONFIG_SPACE;
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#pragma pack()
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VOID
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DumpPciDevice (
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN PCI_TYPE00 *PciData
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)
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{
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//DEBUG ((DEBUG_INFO, " 00/00/00 : [0000][0000] [00|00|00] 00000000 00000000 00000000 00000000 00000000 00000000 0000\n"));
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DEBUG ((DEBUG_INFO, " %02x/%02x/%02x :",
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Bus,
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Device,
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Function
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));
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DEBUG ((DEBUG_INFO, " [%04x][%04x]",
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PciData->Hdr.VendorId,
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PciData->Hdr.DeviceId
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));
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DEBUG ((DEBUG_INFO, " [%02x|%02x|%02x]",
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PciData->Hdr.ClassCode[2],
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PciData->Hdr.ClassCode[1],
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PciData->Hdr.ClassCode[0]
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));
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DEBUG ((DEBUG_INFO, " %08x %08x %08x %08x %08x %08x",
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PciData->Device.Bar[0],
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PciData->Device.Bar[1],
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PciData->Device.Bar[2],
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PciData->Device.Bar[3],
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PciData->Device.Bar[4],
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PciData->Device.Bar[6]
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));
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DEBUG ((DEBUG_INFO, " %04x\n",
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PciData->Hdr.Command
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));
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}
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VOID
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DumpPciBridge (
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN PCI_TYPE01 *PciData
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)
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{
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//DEBUG ((DEBUG_INFO, " 00/00/00*: [0000][0000] [00|00|00] 00000000 00000000 [00|00|00] [00:00] [0000:0000] [0000:0000] [00000000:00000000] [0000:0000] 0000 0000\n"));
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DEBUG ((DEBUG_INFO, " %02x/%02x/%02x*:",
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Bus,
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Device,
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Function
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));
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DEBUG ((DEBUG_INFO, " [%04x][%04x]",
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PciData->Hdr.VendorId,
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PciData->Hdr.DeviceId
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));
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DEBUG ((DEBUG_INFO, " [%02x|%02x|%02x]",
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PciData->Hdr.ClassCode[2],
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PciData->Hdr.ClassCode[1],
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PciData->Hdr.ClassCode[0]
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));
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DEBUG ((DEBUG_INFO, " %08x %08x",
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PciData->Bridge.Bar[0],
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PciData->Bridge.Bar[1]
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));
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DEBUG ((DEBUG_INFO, " [%02x|%02x|%02x]",
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PciData->Bridge.PrimaryBus,
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PciData->Bridge.SecondaryBus,
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PciData->Bridge.SubordinateBus
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));
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DEBUG ((DEBUG_INFO, " [00:00] [0000:0000] [0000:0000]",
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PciData->Bridge.IoBase,
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PciData->Bridge.IoLimit,
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PciData->Bridge.MemoryBase,
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PciData->Bridge.MemoryLimit,
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PciData->Bridge.PrefetchableMemoryBase,
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PciData->Bridge.PrefetchableMemoryLimit
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));
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DEBUG ((DEBUG_INFO, " [00000000:00000000] [0000:0000]",
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PciData->Bridge.PrefetchableBaseUpper32,
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PciData->Bridge.PrefetchableLimitUpper32,
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PciData->Bridge.IoBaseUpper16,
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PciData->Bridge.IoLimitUpper16
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));
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DEBUG ((DEBUG_INFO, " %04x ",
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PciData->Bridge.BridgeControl
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));
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DEBUG ((DEBUG_INFO, " %04x\n",
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PciData->Hdr.Command
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));
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}
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/**
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This function gets the protocol interface from the given handle, and
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obtains its address space descriptors.
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@param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
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@param[out] IoDev Handle used to access configuration space of PCI device.
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@param[out] Descriptors Points to the address space descriptors.
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@retval EFI_SUCCESS The command completed successfully
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**/
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EFI_STATUS
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PciGetProtocolAndResource (
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IN EFI_HANDLE Handle,
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OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,
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OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors
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)
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{
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EFI_STATUS Status;
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//
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// Get inferface from protocol
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//
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Status = gBS->HandleProtocol (
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Handle,
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&gEfiPciRootBridgeIoProtocolGuid,
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(VOID**)IoDev
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Call Configuration() to get address space descriptors
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//
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Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);
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if (Status == EFI_UNSUPPORTED) {
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*Descriptors = NULL;
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return EFI_SUCCESS;
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} else {
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return Status;
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}
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}
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/**
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This function get the next bus range of given address space descriptors.
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It also moves the pointer backward a node, to get prepared to be called
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again.
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@param[in, out] Descriptors Points to current position of a serial of address space
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descriptors.
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@param[out] MinBus The lower range of bus number.
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@param[out] MaxBus The upper range of bus number.
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@param[out] IsEnd Meet end of the serial of descriptors.
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@retval EFI_SUCCESS The command completed successfully.
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**/
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EFI_STATUS
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PciGetNextBusRange (
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IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,
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OUT UINT16 *MinBus,
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OUT UINT16 *MaxBus,
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OUT BOOLEAN *IsEnd
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)
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{
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*IsEnd = FALSE;
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//
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// When *Descriptors is NULL, Configuration() is not implemented, so assume
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// range is 0~PCI_MAX_BUS
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//
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if ((*Descriptors) == NULL) {
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*MinBus = 0;
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*MaxBus = PCI_MAX_BUS;
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return EFI_SUCCESS;
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}
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//
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// *Descriptors points to one or more address space descriptors, which
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// ends with a end tagged descriptor. Examine each of the descriptors,
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// if a bus typed one is found and its bus range covers bus, this handle
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// is the handle we are looking for.
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//
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while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {
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if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
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*MinBus = (UINT16) (*Descriptors)->AddrRangeMin;
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*MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;
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(*Descriptors)++;
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return (EFI_SUCCESS);
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}
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(*Descriptors)++;
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}
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if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {
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*IsEnd = TRUE;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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TestPointCheckPciResource (
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VOID
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)
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{
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UINT16 Bus;
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UINT16 Device;
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UINT16 Func;
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UINT64 Address;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;
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EFI_STATUS Status;
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PCI_TYPE00 PciData;
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UINTN Index;
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EFI_HANDLE *HandleBuf;
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UINTN HandleCount;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
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UINT16 MinBus;
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UINT16 MaxBus;
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BOOLEAN IsEnd;
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DEBUG ((DEBUG_INFO, "==== TestPointCheckPciResource - Enter\n"));
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HandleBuf = NULL;
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Status = gBS->LocateHandleBuffer (
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ByProtocol,
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&gEfiPciRootBridgeIoProtocolGuid,
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NULL,
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&HandleCount,
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&HandleBuf
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);
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if (EFI_ERROR (Status)) {
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goto Done ;
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}
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DEBUG ((DEBUG_INFO, " B D F* VID DID Class[CSP] Bar0 Bar1 Bus[PSS] Io[BL] Memory[BL]"));
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DEBUG ((DEBUG_INFO, " PMemory[BL] PMemoryU[BL] IoU[BL] BriCtl Command\n"));
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DEBUG ((DEBUG_INFO, " B D F VID DID Class[CSP] Bar0 Bar1 Bar2 Bar3 Bar4 Bar5 Command\n"));
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for (Index = 0; Index < HandleCount; Index++) {
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Status = PciGetProtocolAndResource (
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HandleBuf[Index],
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&IoDev,
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&Descriptors
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);
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while (TRUE) {
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Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
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if (EFI_ERROR (Status)) {
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goto Done;
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}
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if (IsEnd) {
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break;
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}
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for (Bus = MinBus; Bus <= MaxBus; Bus++) {
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//
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// For each devices, enumerate all functions it contains
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//
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for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
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//
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// For each function, read its configuration space and print summary
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//
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for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
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Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);
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IoDev->Pci.Read (
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IoDev,
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EfiPciWidthUint16,
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Address,
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1,
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&PciData.Hdr.VendorId
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);
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//
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// If VendorId = 0xffff, there does not exist a device at this
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// location. For each device, if there is any function on it,
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// there must be 1 function at Function 0. So if Func = 0, there
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// will be no more functions in the same device, so we can break
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// loop to deal with the next device.
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//
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if (PciData.Hdr.VendorId == 0xffff && Func == 0) {
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break;
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}
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if (PciData.Hdr.VendorId != 0xffff) {
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IoDev->Pci.Read (
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IoDev,
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EfiPciWidthUint32,
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Address,
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sizeof (PciData) / sizeof (UINT32),
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&PciData
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);
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if (IS_PCI_BRIDGE(&PciData)) {
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// Bridge
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DumpPciBridge ((UINT8)Bus, (UINT8)Device, (UINT8)Func, (PCI_TYPE01 *)&PciData);
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} else if (IS_CARDBUS_BRIDGE(&PciData)) {
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// CardBus Bridge
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} else {
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// Device
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DumpPciDevice ((UINT8)Bus, (UINT8)Device, (UINT8)Func, &PciData);
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}
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//
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// If this is not a multi-function device, we can leave the loop
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// to deal with the next device.
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//
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if (Func == 0 && ((PciData.Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {
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break;
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}
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}
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}
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}
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}
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//
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// If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
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// we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
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// devices on all bus, we can leave loop.
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//
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if (Descriptors == NULL) {
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break;
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}
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}
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}
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Done:
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if (HandleBuf != NULL) {
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FreePool (HandleBuf);
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}
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DEBUG ((DEBUG_INFO, "==== TestPointCheckPciResource - Exit\n"));
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if (EFI_ERROR(Status)) {
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TestPointLibAppendErrorString (
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PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV,
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NULL,
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TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_RESOURCE_ALLOCATED_ERROR_CODE \
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TEST_POINT_PCI_ENUMERATION_DONE \
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TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_RESOURCE_ALLOCATED_ERROR_STRING
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);
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}
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return Status;
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}
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EFI_STATUS
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TestPointCheckPciBusMaster (
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VOID
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)
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{
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UINTN Segment;
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UINTN SegmentCount;
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UINTN Bus;
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UINTN Device;
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UINTN Function;
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UINT16 VendorId;
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UINT16 Command;
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UINT8 HeaderType;
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EFI_STATUS Status;
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PCI_SEGMENT_INFO *PciSegmentInfo;
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PciSegmentInfo = GetPciSegmentInfo (&SegmentCount);
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if (PciSegmentInfo == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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Status = EFI_SUCCESS;
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for (Segment = 0; Segment < SegmentCount; Segment++) {
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for (Bus = PciSegmentInfo[Segment].StartBusNumber; Bus <= PciSegmentInfo[Segment].EndBusNumber; Bus++) {
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for (Device = 0; Device <= 0x1F; Device++) {
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for (Function = 0; Function <= 0x7; Function++) {
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VendorId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS(PciSegmentInfo[Segment].SegmentNumber, Bus, Device, Function, PCI_VENDOR_ID_OFFSET));
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//
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// If VendorId = 0xffff, there does not exist a device at this
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// location. For each device, if there is any function on it,
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// there must be 1 function at Function 0. So if Func = 0, there
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// will be no more functions in the same device, so we can break
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// loop to deal with the next device.
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//
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if (VendorId == 0xffff && Function == 0) {
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break;
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}
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if (VendorId != 0xffff) {
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Command = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, PCI_COMMAND_OFFSET));
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if ((Command & EFI_PCI_COMMAND_BUS_MASTER) != 0) {
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DEBUG ((DEBUG_INFO, "PCI BME enabled (S%04x.B%02x.D%02x.F%x - %04x)\n", Segment, Bus, Device, Function, Command));
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TestPointLibAppendErrorString (
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PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV,
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NULL,
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TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_BUS_MASTER_DISABLED_ERROR_CODE \
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TEST_POINT_PCI_ENUMERATION_DONE \
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TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_BUS_MASTER_DISABLED_ERROR_STRING
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);
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Status = EFI_INVALID_PARAMETER;
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}
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//
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// If this is not a multi-function device, we can leave the loop
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// to deal with the next device.
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//
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HeaderType = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, PCI_HEADER_TYPE_OFFSET));
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if (Function == 0 && ((HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {
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break;
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}
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}
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}
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}
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}
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}
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return Status;
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}
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