/** @file
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PciHostBridge Library
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiDxe.h>
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#include <IndustryStandard/Pci.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Library/PciHostBridgeLib.h>
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GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
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L"Mem", L"I/O", L"Bus"
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};
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ACPI_HID_DEVICE_PATH mRootBridgeDeviceNodeTemplate = {
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{
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ACPI_DEVICE_PATH,
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ACPI_DP,
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{
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(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),
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(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8)
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}
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},
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EISA_PNP_ID (0x0A03),
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0
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};
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PCI_ROOT_BRIDGE mRootBridgeTemplate = {
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0,
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EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
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EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
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EFI_PCI_ATTRIBUTE_ISA_IO |
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EFI_PCI_ATTRIBUTE_ISA_IO_16 |
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EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO |
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EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 |
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EFI_PCI_ATTRIBUTE_VGA_MEMORY |
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EFI_PCI_ATTRIBUTE_VGA_IO |
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EFI_PCI_ATTRIBUTE_VGA_IO_16, // Supports;
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0, // Attributes;
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FALSE, // DmaAbove4G;
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FALSE, // NoExtendedConfigSpace;
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FALSE, // ResourceAssigned;
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EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM, // AllocationAttributes
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{ 0, 255 }, // Bus
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{ 0, 0 }, // Io - to be fixed later
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{ 0, 0 }, // Mem - to be fixed later
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{ 0, 0 }, // MemAbove4G - to be fixed later
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{ 0, 0 }, // PMem - COMBINE_MEM_PMEM indicating no PMem and PMemAbove4GB
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{ 0, 0 }, // PMemAbove4G
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NULL // DevicePath;
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};
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/**
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Return all the root bridge instances.
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@param Count Return the count of root bridge instances.
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@return All the root bridge instances, it will be NULL if system has insufficient memory
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resources available and count will be zero.
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**/
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PCI_ROOT_BRIDGE *
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EFIAPI
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PciHostBridgeGetRootBridges (
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UINTN *Count
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)
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{
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UINT8 Index;
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PCI_ROOT_BRIDGE *RootBridge;
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RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE) * PcdGet8 (PcdPciSegmentCount));
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if (RootBridge == NULL) {
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DEBUG ((DEBUG_ERROR, "PciHostBridge: Out of resource\n"));
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*Count = 0;
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return RootBridge;
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}
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mRootBridgeTemplate.Mem.Base = PcdGet32 (PcdPciReservedMemBase);
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if (PcdGet32(PcdPciReservedMemLimit) != 0) {
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mRootBridgeTemplate.Mem.Limit = PcdGet32 (PcdPciReservedMemLimit);
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} else {
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mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64 (PcdPciExpressBaseAddress) - 1;
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}
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mRootBridgeTemplate.MemAbove4G.Base = PcdGet64 (PcdPciReservedMemAbove4GBBase);
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mRootBridgeTemplate.MemAbove4G.Limit = PcdGet64 (PcdPciReservedMemAbove4GBLimit);
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mRootBridgeTemplate.PMem.Base = PcdGet32 (PcdPciReservedPMemBase);
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mRootBridgeTemplate.PMem.Limit = PcdGet32 (PcdPciReservedPMemLimit);
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mRootBridgeTemplate.PMemAbove4G.Base = PcdGet64 (PcdPciReservedPMemAbove4GBBase);
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mRootBridgeTemplate.PMemAbove4G.Limit = PcdGet64 (PcdPciReservedPMemAbove4GBLimit);
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if (mRootBridgeTemplate.MemAbove4G.Base < mRootBridgeTemplate.MemAbove4G.Limit) {
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mRootBridgeTemplate.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
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}
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mRootBridgeTemplate.Io.Base = PcdGet16 (PcdPciReservedIobase);
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mRootBridgeTemplate.Io.Limit = PcdGet16 (PcdPciReservedIoLimit);
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mRootBridgeTemplate.DmaAbove4G = PcdGetBool (PcdPciDmaAbove4G);
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mRootBridgeTemplate.NoExtendedConfigSpace = PcdGetBool (PcdPciNoExtendedConfigSpace);
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mRootBridgeTemplate.ResourceAssigned = PcdGetBool (PcdPciResourceAssigned);
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for (Index = 0; Index < PcdGet8 (PcdPciSegmentCount); Index ++) {
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mRootBridgeDeviceNodeTemplate.UID = Index;
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mRootBridgeTemplate.Segment = Index;
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mRootBridgeTemplate.DevicePath = NULL;
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mRootBridgeTemplate.DevicePath = AppendDevicePathNode (NULL, &mRootBridgeDeviceNodeTemplate.Header);
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CopyMem (RootBridge + Index, &mRootBridgeTemplate, sizeof (PCI_ROOT_BRIDGE));
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}
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*Count = PcdGet8 (PcdPciSegmentCount);
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return RootBridge;
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}
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VOID
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EFIAPI
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PciHostBridgeFreeRootBridges (
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PCI_ROOT_BRIDGE *Bridges,
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UINTN Count
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)
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{
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ASSERT (Count <= PcdGet8 (PcdPciSegmentCount));
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FreePool (Bridges->DevicePath);
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}
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/**
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Inform the platform that the resource conflict happens.
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@param HostBridgeHandle Handle of the Host Bridge.
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@param Configuration Pointer to PCI I/O and PCI memory resource descriptors.
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The Configuration contains the resources for all the
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root bridges. The resource for each root bridge is
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terminated with END descriptor and an additional END
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is appended indicating the end of the whole resources.
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The resource descriptor field values follow the description
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in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SubmitResources().
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**/
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VOID
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EFIAPI
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PciHostBridgeResourceConflict (
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EFI_HANDLE HostBridgeHandle,
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VOID *Configuration
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)
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{
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
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UINTN RootBridgeIndex;
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DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
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RootBridgeIndex = 0;
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
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while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
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DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
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for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
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ASSERT (Descriptor->ResType <
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sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
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);
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DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
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mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], Descriptor->AddrLen, Descriptor->AddrRangeMax));
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if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
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DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
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Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
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((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0) ? L" (Prefetchable)" : L""
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));
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}
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}
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//
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// Skip the END descriptor for root bridge
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//
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ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor + 1);
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}
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ASSERT (FALSE);
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}
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