/** @file
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SetCacheMtrr library functions.
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This implementation is for typical platforms and may not be
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needed when cache MTRR will be initialized by FSP.
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <PiPei.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MtrrLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Guid/SmramMemoryReserve.h>
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/**
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Set Cache Mtrr.
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**/
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VOID
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EFIAPI
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SetCacheMtrr (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_PEI_HOB_POINTERS Hob;
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MTRR_SETTINGS MtrrSetting;
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UINT64 MemoryBase;
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UINT64 MemoryLength;
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UINT64 LowMemoryLength;
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UINT64 HighMemoryLength;
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EFI_BOOT_MODE BootMode;
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EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
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UINT64 CacheMemoryLength;
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///
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/// Reset all MTRR setting.
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///
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ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
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///
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/// Cache the Flash area as WP to boost performance
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///
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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(UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
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(UINTN) PcdGet32 (PcdFlashAreaSize),
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CacheWriteProtected
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);
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ASSERT_EFI_ERROR (Status);
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///
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/// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
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///
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MtrrSetAllMtrrs (&MtrrSetting);
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///
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/// Set low to 1 MB. Since 1MB cacheability will always be set
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/// until override by CSM.
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/// Initialize high memory to 0.
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///
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LowMemoryLength = 0x100000;
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HighMemoryLength = 0;
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ResourceAttribute = (
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
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);
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Status = PeiServicesGetBootMode (&BootMode);
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ASSERT_EFI_ERROR (Status);
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if (BootMode != BOOT_ON_S3_RESUME) {
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ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
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}
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Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
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while (!END_OF_HOB_LIST (Hob)) {
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if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
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if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
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((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
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(Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
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) {
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if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
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HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
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} else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
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LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
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}
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}
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}
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Hob.Raw = GET_NEXT_HOB (Hob);
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}
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DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
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DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
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///
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/// Assume size of main memory is multiple of 256MB
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///
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MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
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MemoryBase = 0;
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CacheMemoryLength = MemoryLength;
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///
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/// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
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///
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if (MemoryLength > 0xDC000000) {
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CacheMemoryLength = 0xC0000000;
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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MemoryBase,
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CacheMemoryLength,
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CacheWriteBack
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);
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ASSERT_EFI_ERROR (Status);
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MemoryBase = 0xC0000000;
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CacheMemoryLength = MemoryLength - 0xC0000000;
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if (MemoryLength > 0xE0000000) {
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CacheMemoryLength = 0x20000000;
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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MemoryBase,
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CacheMemoryLength,
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CacheWriteBack
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);
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ASSERT_EFI_ERROR (Status);
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MemoryBase = 0xE0000000;
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CacheMemoryLength = MemoryLength - 0xE0000000;
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}
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}
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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MemoryBase,
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CacheMemoryLength,
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CacheWriteBack
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);
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ASSERT_EFI_ERROR (Status);
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if (LowMemoryLength != MemoryLength) {
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MemoryBase = LowMemoryLength;
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MemoryLength -= LowMemoryLength;
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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MemoryBase,
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MemoryLength,
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CacheUncacheable
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);
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ASSERT_EFI_ERROR (Status);
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}
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///
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/// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
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///
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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0xA0000,
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0x20000,
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CacheUncacheable
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);
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ASSERT_EFI_ERROR (Status);
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///
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/// Update MTRR setting from MTRR buffer
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///
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MtrrSetAllMtrrs (&MtrrSetting);
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return ;
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}
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/**
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Update MTRR setting in EndOfPei phase.
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This function will clear temporary memory (CAR) phase MTRR settings
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and configure MTRR to cover permanent memory.
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@retval EFI_SUCCESS The function completes successfully.
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@retval Others Some error occurs.
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**/
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EFI_STATUS
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EFIAPI
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SetCacheMtrrAfterEndOfPei (
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VOID
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)
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{
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EFI_STATUS Status;
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MTRR_SETTINGS MtrrSetting;
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EFI_PEI_HOB_POINTERS Hob;
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UINT64 MemoryBase;
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UINT64 MemoryLength;
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UINT64 Power2Length;
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EFI_BOOT_MODE BootMode;
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UINTN Index;
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UINT64 SmramSize;
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UINT64 SmramBase;
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EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
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Status = PeiServicesGetBootMode (&BootMode);
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ASSERT_EFI_ERROR (Status);
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if (BootMode == BOOT_ON_S3_RESUME) {
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return EFI_SUCCESS;
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}
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//
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// Clear the CAR Settings
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//
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ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
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//
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// Default Cachable attribute will be set to WB to support large memory size/hot plug memory
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//
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MtrrSetting.MtrrDefType &= ~((UINT64)(0xFF));
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MtrrSetting.MtrrDefType |= (UINT64) CacheWriteBack;
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//
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// Set fixed cache for memory range below 1MB
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//
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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0x0,
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0xA0000,
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CacheWriteBack
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);
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ASSERT_EFI_ERROR (Status);
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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0xA0000,
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0x20000,
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CacheUncacheable
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);
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ASSERT_EFI_ERROR (Status);
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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0xC0000,
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0x40000,
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CacheWriteProtected
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);
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ASSERT_EFI_ERROR ( Status);
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//
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// PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
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// Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
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//
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SmramSize = 0;
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SmramBase = 0;
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Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
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while (!END_OF_HOB_LIST (Hob)) {
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if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
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if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
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SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
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for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
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if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
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SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
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if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
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SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
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}
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}
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}
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break;
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}
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}
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Hob.Raw = GET_NEXT_HOB (Hob);
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}
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//
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// Set non system memory as UC
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//
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MemoryBase = 0x100000000;
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//
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// Add IED size to set whole SMRAM as WB to save MTRR count
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//
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MemoryLength = MemoryBase - (SmramBase + SmramSize);
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while (MemoryLength != 0) {
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Power2Length = GetPowerOfTwo64 (MemoryLength);
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MemoryBase -= Power2Length;
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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MemoryBase,
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Power2Length,
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CacheUncacheable
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);
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ASSERT_EFI_ERROR (Status);
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MemoryLength -= Power2Length;
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}
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DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
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DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
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if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReservedMemAbove4GBBase)) {
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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PcdGet64 (PcdPciReservedMemAbove4GBBase),
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PcdGet64 (PcdPciReservedMemAbove4GBLimit) - PcdGet64 (PcdPciReservedMemAbove4GBBase) + 1,
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CacheUncacheable
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);
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ASSERT_EFI_ERROR ( Status);
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}
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DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBLimit)));
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DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBBase)));
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if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReservedPMemAbove4GBBase)) {
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Status = MtrrSetMemoryAttributeInMtrrSettings (
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&MtrrSetting,
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PcdGet64 (PcdPciReservedPMemAbove4GBBase),
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PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - PcdGet64 (PcdPciReservedPMemAbove4GBBase) + 1,
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CacheUncacheable
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);
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ASSERT_EFI_ERROR ( Status);
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}
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//
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// Update MTRR setting from MTRR buffer
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//
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MtrrSetAllMtrrs (&MtrrSetting);
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return Status;
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}
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