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| /** @file
| Provide TempRamInitParams data.
|
| Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
| SPDX-License-Identifier: BSD-2-Clause-Patent
|
| **/
|
| #include <Library/PcdLib.h>
| #include <FspEas.h>
| #include "FsptCoreUpd.h"
|
| typedef struct {
| FSP_UPD_HEADER FspUpdHeader;
| FSPT_CORE_UPD FsptCoreUpd;
| } FSPT_UPD_CORE_DATA;
|
| GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {
| {
| 0x4450555F54505346,
| 0x00,
| { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
| }
| },
| {
| FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv),
| FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv),
| 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
| FixedPcdGet32 (PcdFlashCodeCacheSize),
| { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
| }
| }
| };
|
|
|
