## @file
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# PCD configuration build description file for the KabylakeRvp3 board.
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#
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# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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################################################################################
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#
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# Pcd Section - list of all PCD Entries used by this board.
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#
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################################################################################
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[PcdsFixedAtBuild.common]
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######################################
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# Key Boot Stage and FSP configuration
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######################################
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#
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# Please select the Boot Stage here.
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# Stage 1 - enable debug (system deadloop after debug init)
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# Stage 2 - mem init (system deadloop after mem init)
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# Stage 3 - boot to shell only
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# Stage 4 - boot to OS
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# Stage 5 - boot to OS with security boot enabled
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# Stage 6 - boot with advanced features enabled
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#
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gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
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#
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# 0: FSP Wrapper is running in Dispatch mode.
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# 1: FSP Wrapper is running in API mode.
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
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#
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# FALSE: The board is not a FSP wrapper (FSP binary not used)
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# TRUE: The board is a FSP wrapper (FSP binary is used)
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#
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gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
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#
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# FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
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# (both inside FSP and outside FSP).
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# Pros:
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# * PEI Main is re-built from source and is always the latest version
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# * Platform code can link any desired LibraryClass to PEI Main
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# (Ex: Custom DebugLib instance, SerialPortLib, etc.)
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# Cons:
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# * The PEI Main being used to execute FSP PEIMs is not the PEI Main
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# that the FSP PEIMs were tested with, adding risk of breakage.
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# * Two copies of PEI Main will exist in the final binary,
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# #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
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# executed, wasting space.
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#
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# <b>TRUE</b>: The PEI Main included in FSP is used to dispatch all PEIMs
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# (both inside FSP and outside FSP). PEI Main will not be included in
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# FvPreMemory. This is the default and is the recommended choice.
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#
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gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
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#
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# FSP Base address PCD will be updated in FDF basing on flash map.
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
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gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
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gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
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gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
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!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
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#
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# FSP API mode does not share stack with the boot loader,
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# so FSP needs more temporary memory for FSP heap + stack size.
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#
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gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
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#
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# FSP API mode does not need to enlarge the boot loader stack size
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# since the stacks are separate.
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#
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gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
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!else
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#
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# In FSP Dispatch mode boot loader stack size must be large
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# enough for executing both boot loader and FSP.
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#
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gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000
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!endif
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!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
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gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
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gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
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!else
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#
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# FSP Dispatch mode requires more platform memory as boot loader and FSP sharing the same
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# platform memory.
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#
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gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000
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!endif
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[PcdsFeatureFlag.common]
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######################################
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# Edk2 Configuration
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######################################
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gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
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######################################
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# Silicon Configuration
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######################################
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# Build switches
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gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
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# CPU
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gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE
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# SA
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gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
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# ME
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gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
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# Others
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gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
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gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
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######################################
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# Platform Configuration
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######################################
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
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gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
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gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
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!endif
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!if $(TARGET) == DEBUG
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gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
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!else
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gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
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!endif
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######################################
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# Board Configuration
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######################################
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gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE
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gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE
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[PcdsFixedAtBuild.common]
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######################################
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# Edk2 Configuration
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######################################
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!if $(TARGET) == RELEASE
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
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!else
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
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!endif
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
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!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
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gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
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!endif
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gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
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gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
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gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
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!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
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!endif
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
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gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
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!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
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!endif
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gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
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!if $(TARGET) == DEBUG
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
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!endif
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
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!if $(TARGET) == RELEASE
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
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!else
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
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!endif
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
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# Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
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!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
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#
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# In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
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# (They will be DynamicEx in FSP Dispatch mode)
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#
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## Specifies max supported number of Logical Processors.
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# @Prompt Configure max supported number of Logical Processors
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12
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## Specifies the size of the microcode Region.
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# @Prompt Microcode Region size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
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## Specifies the AP wait loop state during POST phase.
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# The value is defined as below.
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# 1: Place AP in the Hlt-Loop state.
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# 2: Place AP in the Mwait-Loop state.
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# 3: Place AP in the Run-Loop state.
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# @Prompt The AP wait loop state.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
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!endif
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######################################
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# Silicon Configuration
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######################################
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# Refer to HstiFeatureBit.h for bit definitions
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gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
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gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
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######################################
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# Platform Configuration
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######################################
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
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gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
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#
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# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
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#
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# BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
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# BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
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# that lie entirely within the expected fixed memory regions.
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# BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
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# BIT3-31: Reserved
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#
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gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
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!if $(TARGET) == RELEASE
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
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!else
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
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!endif
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
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!if $(TARGET) == RELEASE
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
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!else
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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######################################
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# Board Configuration
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######################################
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gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|1
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gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00, 0x1F, 0x00}
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[PcdsFixedAtBuild.IA32]
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######################################
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# Edk2 Configuration
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######################################
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gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
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gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
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gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
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######################################
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# Platform Configuration
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######################################
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gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
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[PcdsFixedAtBuild.X64]
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######################################
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# Edk2 Configuration
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######################################
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# Default platform supported RFC 4646 languages: (American) English
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gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
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[PcdsPatchableInModule.common]
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######################################
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# Edk2 Configuration
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######################################
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
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gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
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|
######################################
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# Silicon Configuration
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######################################
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!if $(TARGET) == DEBUG
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gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
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!endif
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|
[PcdsDynamicDefault]
|
######################################
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# Edk2 Configuration
|
######################################
|
gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
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|
#
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# Set video to native resolution as Windows 8 WHCK requirement.
|
#
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
|
|
gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0
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gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F
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gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
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gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
|
|
#
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# FSP Base address PCD will be updated in FDF basing on flash map.
|
#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
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# Platform will pre-allocate UPD buffer and pass it to FspWrapper
|
# Those dummy address will be patched before FspWrapper executing
|
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF
|
|
######################################
|
# Board Configuration
|
######################################
|
|
# Thunderbolt Configuration
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
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gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0
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gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011
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gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerEn|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerType|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
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gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioAccessType|0x2
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemRsvd|100
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
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gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWin10Support|0x0
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExpander|0x0
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000001
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0
|
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtOffDelay|5000
|
|
[PcdsDynamicHii.X64.DEFAULT]
|
######################################
|
# Edk2 Configuration
|
######################################
|
gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
|
!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
|
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
|
!else
|
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
|
!endif
|
