/** @file
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Definition for supported EC commands.
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef EC_COMMANDS_H_
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#define EC_COMMANDS_H_
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//
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// Timeout if EC command/data fails
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//
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#define EC_TIME_OUT 0x20000
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//
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// The EC implements an embedded controller interface at ports 0x60/0x64 and a ACPI compliant
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// system management controller at ports 0x62/0x66. Port 0x66 is the command and status port,
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// port 0x62 is the data port.
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//
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#define EC_D_PORT 0x62
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#define EC_C_PORT 0x66
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//
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// Status Port 0x62
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//
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#define EC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the threshold
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#define EC_S_SMI_EVT 0x40 // SMI event is pending
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#define EC_S_SCI_EVT 0x20 // SCI event is pending
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#define EC_S_BURST 0x10 // EC is in burst mode or normal mode
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#define EC_S_CMD 0x08 // Byte in data register is command/data
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#define EC_S_IGN 0x04 // Ignored
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#define EC_S_IBF 0x02 // Input buffer is full/empty
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#define EC_S_OBF 0x01 // Output buffer is full/empty
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//
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// EC commands that are issued to the EC through the command port (0x66).
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// New commands and command parameters should only be written by the host when IBF=0.
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// Data read from the EC data port is valid only when OBF=1.
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//
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#define EC_C_FAB_ID 0x0D // Get the board fab ID in the lower 3 bits
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#define EC_C_ACPI_READ 0x80 // Read a byte of EC RAM
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#define EC_C_ACPI_WRITE 0x81 // Write a byte of EC RAM
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#endif // EC_COMMANDS_H_
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