/** @file
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Platform Hook Library
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/PlatformHookLib.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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#include <Library/PcdLib.h>
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#include <SystemAgent/Include/SaAccess.h>
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#include <SioRegs.h>
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#include <Library/MmPciLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Register/PchRegsLpc.h>
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#include <PchAccess.h>
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#define COM1_BASE 0x3f8
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#define COM2_BASE 0x2f8
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#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690
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#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E
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#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F
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#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20
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#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E
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#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F
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#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E
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#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F
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typedef struct {
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UINT8 Register;
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UINT8 Value;
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} EFI_SIO_TABLE;
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] = {
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{0x002, 0x88}, // Power On UARTs
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{0x024, COM1_BASE >> 2},
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{0x025, COM2_BASE >> 2},
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{0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
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{0x029, 0x080}, // SIRQ_CLKRUN_EN
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{0x02A, 0x000},
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{0x02B, 0x0DE},
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{0x00A, 0x040},
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{0x00C, 0x00E},
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{0x02c, 0x002},
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{0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
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{0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
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{0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
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{0x03a, 0x00A}, // LPC Docking Enabling
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{0x031, 0x01f},
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{0x032, 0x000},
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{0x033, 0x004},
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{0x038, 0x0FB},
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{0x035, 0x0FE},
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{0x036, 0x000},
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{0x037, 0x0FF},
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{0x039, 0x000},
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{0x034, 0x001},
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{0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF}, // Relocate configuration ports base address
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{0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF} // to ensure SIO config address can be accessed in OS
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};
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[] = {
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{0x002, 0x88}, // Power On UARTs
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{0x007, 0x00},
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{0x024, COM1_BASE >> 2},
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{0x025, COM2_BASE >> 2},
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{0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
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{0x029, 0x080}, // SIRQ_CLKRUN_EN
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{0x02A, 0x000},
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{0x02B, 0x0DE},
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{0x00A, 0x040},
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{0x00C, 0x00E},
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{0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
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{0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
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{0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
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{0x03a, 0x00A}, // LPC Docking Enabling
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{0x031, 0x01f},
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{0x032, 0x000},
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{0x033, 0x004},
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{0x038, 0x0FB},
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{0x035, 0x0FE},
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{0x036, 0x000},
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{0x037, 0x0FE},
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{0x039, 0x000},
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{0x034, 0x001}
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};
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] = {
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{0x29, 0x0A0}, // Enable super I/O clock and set to 48MHz
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{0x22, 0x003}, //
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{0x07, 0x003}, // Select UART0 device
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{0x60, (COM1_BASE >> 8)}, // Set Base Address MSB
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{0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB
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{0x70, 0x004}, // Set to IRQ4
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{0x30, 0x001}, // Enable it with Activation bit
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{0x07, 0x002}, // Select UART1 device
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{0x60, (COM2_BASE >> 8)}, // Set Base Address MSB
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{0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB
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{0x70, 0x003}, // Set to IRQ3
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{0x30, 0x001}, // Enable it with Activation bit
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{0x07, 0x007}, // Select GPIO device
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{0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Address MSB
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{0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base Address LSB
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{0x30, 0x001}, // Enable it with Activation bit
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{0x21, 0x001}, // Global Device Enable
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{0x26, 0x000} // Fast Enable UART 0 & 1 as their enable & activation bit
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};
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//
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// National PC8374L
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//
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] = {
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{0x007, 0x03}, // Select Com1
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{0x061, 0xF8}, // 0x3F8
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{0x060, 0x03}, // 0x3F8
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{0x070, 0x04}, // IRQ4
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{0x030, 0x01} // Active
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};
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//
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// IT8628
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//
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = {
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{0x023, 0x09}, // Clock Selection register
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{0x007, 0x01}, // Com1 Logical Device Number select
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{0x061, 0xF8}, // Serial Port 1 Base Address MSB Register
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{0x060, 0x03}, // Serial Port 1 Base Address LSB Register
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{0x070, 0x04}, // Serial Port 1 Interrupt Level Select
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{0x030, 0x01}, // Serial Port 1 Activate
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{0x007, 0x02}, // Com1 Logical Device Number select
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{0x061, 0xF8}, // Serial Port 2 Base Address MSB Register
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{0x060, 0x02}, // Serial Port 2 Base Address MSB Register
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{0x070, 0x03}, // Serial Port 2 Interrupt Level Select
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{0x030, 0x01} // Serial Port 2 Activate
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};
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableParallelPort[] = {
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{0x007, 0x03}, // Parallel Port Logical Device Number select
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{0x030, 0x00}, // Parallel port Activate
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{0x061, 0x78}, // Parallel Port Base Address 1 MSB Register
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{0x060, 0x03}, // Parallel Port Base Address 1 LSB Register
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{0x063, 0x78}, // Parallel Port Base Address 2 MSB Register
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{0x062, 0x07}, // Parallel Port Base Address 1 LSB Register
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{0x0F0, 0x03} // Special Configuration register
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};
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbondX374[] = {
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{0x07, 0x03}, // Select UART0 device
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{0x60, (COM1_BASE >> 8)}, // Set Base Address MSB
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{0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB
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{0x70, 0x04}, // Set to IRQ4
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{0x30, 0x01} // Enable it with Activation bit
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};
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] = {
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{0x07, 0x02}, // Set logical device SP Serial port Com0
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{0x61, 0xF8}, // Write Base Address LSB register 0x3F8
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{0x60, 0x03}, // Write Base Address MSB register 0x3F8
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{0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard
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{0x30, 0x01} // Enable serial port with Activation bit
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};
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/**
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Detect if a National 393 SIO is docked. If yes, enable the docked SIO
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and its serial port, and disable the onboard serial port.
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@retval EFI_SUCCESS Operations performed successfully.
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**/
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STATIC
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VOID
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CheckNationalSio (
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VOID
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)
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{
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UINT8 Data8;
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//
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// Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).
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// We use (0x2e, 0x2f) which is determined by BADD default strapping
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//
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//
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// Read the Pc87393 signature
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//
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IoWrite8 (0x2e, 0x20);
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Data8 = IoRead8 (0x2f);
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if (Data8 == 0xea) {
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//
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// Signature matches - National PC87393 SIO is docked
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//
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//
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// Enlarge the LPC decode scope to accommodate the Docking LPC Switch
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// Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at
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// SIO_BASE_ADDRESS + 0x10)
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//
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PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20);
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//
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// Enable port switch
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//
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IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);
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//
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// Turn on docking power
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//
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IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);
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IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);
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IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);
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//
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// Enable port switch
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//
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IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);
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//
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// GPIO setting
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//
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IoWrite8 (0x2e, 0x24);
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IoWrite8 (0x2f, 0x29);
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//
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// Enable chip clock
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//
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IoWrite8 (0x2e, 0x29);
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IoWrite8 (0x2f, 0x1e);
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//
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// Enable serial port
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//
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//
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// Select com1
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//
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IoWrite8 (0x2e, 0x7);
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IoWrite8 (0x2f, 0x3);
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//
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// Base address: 0x3f8
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//
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IoWrite8 (0x2e, 0x60);
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IoWrite8 (0x2f, 0x03);
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IoWrite8 (0x2e, 0x61);
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IoWrite8 (0x2f, 0xf8);
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//
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// Interrupt: 4
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//
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IoWrite8 (0x2e, 0x70);
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IoWrite8 (0x2f, 0x04);
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//
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// Enable bank selection
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//
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IoWrite8 (0x2e, 0xf0);
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IoWrite8 (0x2f, 0x82);
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//
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// Activate
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//
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IoWrite8 (0x2e, 0x30);
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IoWrite8 (0x2f, 0x01);
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//
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// Disable onboard serial port
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//
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IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);
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//
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// Power Down UARTs
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//
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IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);
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IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);
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//
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// Dissable COM1 decode
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//
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IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);
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IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
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//
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// Disable COM2 decode
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//
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IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);
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IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
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//
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// Disable interrupt
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//
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IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);
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IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);
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IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
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//
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// Enable floppy
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//
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//
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// Select floppy
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//
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IoWrite8 (0x2e, 0x7);
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IoWrite8 (0x2f, 0x0);
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//
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// Base address: 0x3f0
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//
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IoWrite8 (0x2e, 0x60);
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IoWrite8 (0x2f, 0x03);
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IoWrite8 (0x2e, 0x61);
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IoWrite8 (0x2f, 0xf0);
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//
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// Interrupt: 6
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//
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IoWrite8 (0x2e, 0x70);
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IoWrite8 (0x2f, 0x06);
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//
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// DMA 2
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//
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IoWrite8 (0x2e, 0x74);
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IoWrite8 (0x2f, 0x02);
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//
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// Activate
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//
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IoWrite8 (0x2e, 0x30);
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IoWrite8 (0x2f, 0x01);
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} else {
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//
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// No National pc87393 SIO is docked, turn off dock power and
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// disable port switch
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//
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// IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);
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// IoWrite8 (0x690, 0);
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//
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// If no National pc87393, just return
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//
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return;
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}
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}
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/**
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Check whether the IT8628 SIO present on LPC. If yes, enable its serial
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ports, parallel port, and port 80.
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@retval EFI_SUCCESS Operations performed successfully.
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**/
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STATIC
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VOID
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It8628SioSerialPortInit (
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VOID
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)
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{
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UINT8 ChipId0 = 0;
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UINT8 ChipId1 = 0;
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UINT16 LpcIoDecondeRangeSet = 0;
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UINT16 LpcIoDecoodeSet = 0;
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UINT8 Index;
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UINTN LpcBaseAddr;
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//
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// Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh.
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//
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LpcBaseAddr = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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LpcIoDecondeRangeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOD);
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LpcIoDecoodeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE);
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MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet | ((V_PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8)));
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MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | (B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE)));
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//
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// Enter MB PnP Mode
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//
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IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87);
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IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01);
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IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
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IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
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//
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// Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)
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//
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IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);
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ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
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IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);
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ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
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//
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// Enable Serial Port 1, Port 2
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//
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if ((ChipId0 == 0x86) && (ChipId1 == 0x28)) {
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for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof (EFI_SIO_TABLE); Index++) {
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IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Register);
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IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Value);
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}
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}
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//
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// Exit MB PnP Mode
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//
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IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02);
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IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02);
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return;
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}
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/**
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Performs platform specific initialization required for the CPU to access
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the hardware associated with a SerialPortLib instance. This function does
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not initialize the serial port hardware itself. Instead, it initializes
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hardware devices that are required for the CPU to access the serial port
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hardware. This function may be called more than once.
|
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@retval RETURN_SUCCESS The platform specific initialization succeeded.
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@retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
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**/
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RETURN_STATUS
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EFIAPI
|
PlatformHookSerialPortInitialize (
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VOID
|
)
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{
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UINT16 ConfigPort;
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UINT16 IndexPort;
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UINT16 DataPort;
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UINT16 DeviceId;
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UINT8 Index;
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UINT16 AcpiBase;
|
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//
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// Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit
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// in ACPI Controll (Reg#44h bit7) for PrePpiStall function use.
|
//
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IndexPort = 0;
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DataPort = 0;
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Index = 0;
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AcpiBase = 0;
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PchAcpiBaseGet (&AcpiBase);
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if (AcpiBase == 0) {
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PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));
|
}
|
|
//
|
// Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
|
//
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PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
|
PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
|
|
// Configure Sio IT8628
|
It8628SioSerialPortInit ();
|
|
DeviceId = MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID);
|
if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) {
|
//
|
// if no EC, it is SV Bidwell Bar board
|
//
|
if ((IoRead8 (0x66) != 0xFF) && (IoRead8 (0x62) != 0xFF)) {
|
//
|
// Super I/O initialization for SMSC SI1007
|
//
|
ConfigPort = FixedPcdGet16 (PcdLpcSioConfigDefaultPort);
|
DataPort = PcdGet16 (PcdLpcSioDataDefaultPort);
|
IndexPort = PcdGet16 (PcdLpcSioIndexDefaultPort);
|
|
//
|
// 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
|
//
|
PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x10);
|
|
//
|
// Program and Enable Default Super IO Configuration Port Addresses and range
|
//
|
PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
|
|
//
|
// Enter Config Mode
|
//
|
IoWrite8 (ConfigPort, 0x55);
|
|
//
|
// Check for SMSC SIO1007
|
//
|
IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register is 0x0D
|
if (IoRead8 (DataPort) == 0x20) { // SMSC SIO1007 Device ID is 0x20
|
//
|
// Configure SIO
|
//
|
for (Index = 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TABLE); Index++) {
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IoWrite8 (IndexPort, mSioTable[Index].Register);
|
IoWrite8 (DataPort, mSioTable[Index].Value);
|
}
|
|
//
|
// Exit Config Mode
|
//
|
IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
|
|
//
|
// GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of CRB_SCH
|
//
|
IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f);
|
}
|
|
//
|
// Check if a National Pc87393 SIO is docked
|
//
|
CheckNationalSio ();
|
|
//
|
// Super I/O initialization for SMSC SIO1000
|
//
|
ConfigPort = PcdGet16 (PcdLpcSioIndexPort);
|
IndexPort = PcdGet16 (PcdLpcSioIndexPort);
|
DataPort = PcdGet16 (PcdLpcSioDataPort);
|
|
//
|
// Enter Config Mode
|
//
|
IoWrite8 (ConfigPort, 0x55);
|
|
//
|
// Check for SMSC SIO1000
|
//
|
if (IoRead8 (ConfigPort) != 0xFF) {
|
//
|
// Configure SIO
|
//
|
for (Index = 0; Index < sizeof (mSioTableSmsc1000) / sizeof (EFI_SIO_TABLE); Index++) {
|
IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register);
|
IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value);
|
}
|
|
//
|
// Exit Config Mode
|
//
|
IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
|
}
|
|
//
|
// Super I/O initialization for Winbond WPCN381U
|
//
|
IndexPort = LPC_SIO_INDEX_DEFAULT_PORT_2;
|
DataPort = LPC_SIO_DATA_DEFAULT_PORT_2;
|
|
//
|
// Check for Winbond WPCN381U
|
//
|
IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID register is 0x20
|
if (IoRead8 (DataPort) == 0xF4) { // Winbond WPCN381U Device ID is 0xF4
|
//
|
// Configure SIO
|
//
|
for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
|
IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
|
IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
|
}
|
}
|
} //EC is not exist, skip mobile board detection for SV board
|
|
//
|
//add for SV Bidwell Bar board
|
//
|
if (IoRead8 (COM1_BASE) == 0xFF) {
|
//
|
// Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC)
|
// Looking for LDC2 card first
|
//
|
IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55);
|
if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) == 0x55) {
|
IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
|
DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
|
} else {
|
IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
|
DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
|
}
|
|
IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20
|
if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1
|
for (Index = 0; Index < sizeof (mSioTableWinbondX374) / sizeof (EFI_SIO_TABLE); Index++) {
|
IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register);
|
IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value);
|
}
|
}
|
}// end of Bidwell Bar SIO initialization
|
} else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || IS_SA_DEVICE_ID_SERVER (DeviceId)) {
|
//
|
// If we are in debug mode, we will allow serial status codes
|
//
|
|
//
|
// National PC8374 SIO & Winbond WPCD374 (LDC2)
|
//
|
IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
|
|
IoWrite8 (IndexPort, 0x55);
|
if (IoRead8 (IndexPort) == 0x55) {
|
IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
|
DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
|
} else {
|
IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
|
DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
|
}
|
|
//
|
// Configure SIO
|
//
|
IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20
|
if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1
|
for (Index = 0; Index < sizeof (mDesktopSioTable) / sizeof (EFI_SIO_TABLE); Index++) {
|
IoWrite8 (IndexPort, mDesktopSioTable[Index].Register);
|
//PrePpiStall (200);
|
IoWrite8 (DataPort, mDesktopSioTable[Index].Value);
|
//PrePpiStall (200);
|
}
|
return RETURN_SUCCESS;
|
}
|
//
|
// Configure Pilot3 SIO
|
//
|
IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config mode.
|
IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); // Pilot3 SIO Device ID register is 0x20.
|
if (IoRead8 (PILOTIII_SIO_DATA_PORT) == PILOTIII_CHIP_ID) { // Pilot3 SIO Device ID register is 0x03.
|
//
|
// Configure SIO
|
//
|
for (Index = 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_SIO_TABLE); Index++) {
|
IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Register);
|
IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value);
|
}
|
}
|
IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mode.
|
}
|
|
|
return RETURN_SUCCESS;
|
}
|
