/**@file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _TBT_SMI_HANDLER_H_
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#define _TBT_SMI_HANDLER_H_
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#include <Library/TbtCommonLib.h>
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#include <Library/IoLib.h>
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#include <IndustryStandard/Pci.h>
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#ifdef PROGRESS_CODE
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#undef PROGRESS_CODE
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#endif
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#define MAX_TBT_DEPTH 6
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#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CLASS_BRIDGE_P2P))
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#define BAR_ALIGN(v, a) ((((v) - 1) | (a)) + 1)
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#define CMD_BUS_MASTER BIT2
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#define CMD_BM_IO (CMD_BUS_MASTER | BIT0)
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#define CMD_BM_MEM (CMD_BUS_MASTER | BIT1)
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#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0)
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#define DEF_CACHE_LINE_SIZE 0x20
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#define DEF_RES_IO_PER_DEV 4
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#define DEF_RES_MEM_PER_DEV 32
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#define DEF_RES_PMEM_PER_DEV 32
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#define DOCK_BUSSES 8
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#define DISBL_IO_REG1C 0x01F1
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#define DISBL_MEM32_REG20 0x0000FFF0
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#define DISBL_PMEM_REG24 0x0001FFF1
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#define count(x) (sizeof (x) / sizeof ((x)[0]))
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#define PCIE_CAP_ID_SSID_SSVID 0x0D
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#define INVALID_PCI_DEVICE 0xFFFFFFFF
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#define PCI_TBT_VESC_REG2 0x510
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typedef struct _PortInfo {
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UINT8 IoBase;
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UINT8 IoLimit;
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UINT16 MemBase;
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UINT16 MemLimit;
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UINT64 PMemBase64;
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UINT64 PMemLimit64;
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UINT8 BusNumLimit;
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UINT8 ConfedEP;
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} PORT_INFO;
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typedef struct _MEM_REGS {
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UINT32 Base;
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UINT32 Limit;
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} MEM_REGS;
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typedef struct _PMEM_REGS {
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UINT64 Base64;
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UINT64 Limit64;
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} PMEM_REGS;
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typedef struct _IO_REGS {
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UINT16 Base;
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UINT16 Limit;
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} IO_REGS;
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typedef struct _BRDG_RES_CONFIG {
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UINT8 Cmd;
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UINT8 Cls;
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UINT8 IoBase;
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UINT8 IoLimit;
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UINT16 MemBase;
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UINT16 MemLimit;
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UINT64 PMemBase64;
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UINT64 PMemLimit64;
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} BRDG_RES_CONFIG;
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typedef struct _BRDG_CONFIG {
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DEV_ID DevId;
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UINT8 PBus;
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UINT8 SBus;
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UINT8 SubBus;
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BOOLEAN IsDSBridge;
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BRDG_RES_CONFIG Res;
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} BRDG_CONFIG;
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enum {
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HR_US_PORT,
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HR_DS_PORT0,
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HR_DS_PORT3,
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HR_DS_PORT4,
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HR_DS_PORT5,
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HR_DS_PORT6,
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MAX_CFG_PORTS
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};
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enum {
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HR_DS_PORT1 = HR_DS_PORT3
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};
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//
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// Alpine Ridge
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//
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enum {
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AR_DS_PORT1 = HR_DS_PORT3,
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AR_DS_PORT2,
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AR_DS_PORT3,
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AR_DS_PORT4
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};
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typedef struct _HR_CONFIG {
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UINT16 DeviceId;
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UINT8 HRBus;
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UINT8 MinDSNumber;
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UINT8 MaxDSNumber;
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UINT8 BridgeLoops;
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} HR_CONFIG;
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STATIC const BRDG_RES_CONFIG NOT_IN_USE_BRIDGE = {
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CMD_BUS_MASTER,
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0,
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DISBL_IO_REG1C & 0xFF,
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DISBL_IO_REG1C >> 8,
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DISBL_MEM32_REG20 & 0xFFFF,
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DISBL_MEM32_REG20 >> 16,
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DISBL_PMEM_REG24 & 0xFFFF,
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DISBL_PMEM_REG24 >> 16
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};
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typedef union _BRDG_CIO_MAP_REG {
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UINT32 AB_REG;
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struct {
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UINT32 NumOfDSPorts : 5;
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UINT32 CioPortMap : 27;
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} Bits;
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} BRDG_CIO_MAP_REG;
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//
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// Functions
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//
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VOID
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ThunderboltCallback (
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IN UINT8 Type
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);
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VOID
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TbtDisablePCIDevicesAndBridges (
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IN UINT8 Type
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);
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VOID
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EndOfThunderboltCallback(
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IN UINTN RpSegment,
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IN UINTN RpBus,
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IN UINTN RpDevice,
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IN UINTN RpFunction
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);
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VOID
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ConfigureTbtAspm(
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IN UINT8 Type,
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IN UINT16 Aspm
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);
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UINT8
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PcieFindCapId (
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IN UINT8 Segment,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT8 CapId
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);
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#endif
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