/**@file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _TBT_COMMON_LIB_H_
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#define _TBT_COMMON_LIB_H_
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#include <Library/BaseLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/GpioExpanderLib.h>
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#define DTBT_CONTROLLER 0x00
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#define DTBT_TYPE_PCH 0x01
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#define DTBT_TYPE_PEG 0x02
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#define TBT2PCIE_DTBT_R 0x548
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#define PCIE2TBT_DTBT_R 0x54C
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//
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// Thunderbolt FW OS capability
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//
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#define NO_OS_NATIVE_SUPPORT 0
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#define OS_NATIVE_SUPPORT_ONLY 1
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#define OS_NATIVE_SUPPORT_RTD3 2
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#define DTBT_SAVE_STATE_OFFSET BIT0 // Bits 0-3 is for DTBT (only bit 0 is in use)
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/**
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Get Tbt2Pcie Register Offset
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@retval Register Register Variable
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**/
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#define GET_TBT2PCIE_REGISTER_ADDRESS(Segment, Bus, Device, Function, RegisterAddress) \
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RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, TBT2PCIE_DTBT_R); \
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/**
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Get Pcie2Tbt Register Offset
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@retval Register Register Variable
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**/
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#define GET_PCIE2TBT_REGISTER_ADDRESS(Segment, Bus, Device, Function, RegisterAddress) \
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RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, PCIE2TBT_DTBT_R); \
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#define PCIE2TBT_VLD_B BIT0
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#define TBT2PCIE_DON_R BIT0
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#define TBT_MAIL_BOX_DELAY (100*1000)
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#define TBT_5S_TIMEOUT 50
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#define TBT_1S_TIMEOUT 10
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#define TBT_3S_TIMEOUT 30
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#define PCIE2TBT_GO2SX (0x02 << 1)
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#define PCIE2TBT_GO2SX_NO_WAKE (0x03 << 1)
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#define PCIE2TBT_SX_EXIT_TBT_CONNECTED (0x04 << 1)
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#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1)
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#define PCIE2TBT_OS_UP (0x06 << 1)
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#define PCIE2TBT_SET_SECURITY_LEVEL (0x08 << 1)
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#define PCIE2TBT_GET_SECURITY_LEVEL (0x09 << 1)
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#define PCIE2TBT_CM_AUTH_MODE_ENTER (0x10 << 1)
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#define PCIE2TBT_CM_AUTH_MODE_EXIT (0x11 << 1)
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#define PCIE2TBT_BOOT_ON (0x18 << 1)
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#define PCIE2TBT_BOOT_OFF (0x19 << 1)
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#define PCIE2TBT_USB_ON (0x19 << 1)
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#define PCIE2TBT_GET_ENUMERATION_METHOD (0x1A << 1)
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#define PCIE2TBT_SET_ENUMERATION_METHOD (0x1B << 1)
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#define PCIE2TBT_POWER_CYCLE (0x1C << 1)
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#define PCIE2TBT_PREBOOTACL (0x1E << 1)
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#define CONNECT_TOPOLOGY_COMMAND (0x1F << 1)
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#define RESET_HR_BIT BIT0
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#define ENUMERATE_HR_BIT BIT1
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#define AUTO 0x0
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//
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//Thunder Bolt Device IDs
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//
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//
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// Alpine Ridge HR device IDs
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//
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#define AR_HR_2C 0x1576
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#define AR_HR_4C 0x1578
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#define AR_XHC 0x15B5
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#define AR_XHC_4C 0x15B6
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#define AR_HR_LP 0x15C0
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//
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// Alpine Ridge C0 HR device IDs
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//
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#define AR_HR_C0_2C 0x15DA
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#define AR_HR_C0_4C 0x15D3
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//
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// Titan Ridge HR device IDs
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//
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#define TR_HR_2C 0x15E7
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#define TR_HR_4C 0x15EA
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//
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//End of Thunderbolt(TM) Device IDs
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//
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typedef struct _DEV_ID {
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UINT8 Segment;
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UINT8 Bus;
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UINT8 Dev;
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UINT8 Fun;
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} DEV_ID;
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//@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf
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//@todo should refactor this to only be present in that driver
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//@todo also definitions like this should never be in a .h file anyway
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//@todo this is a quick hack to get things compiling for now
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#ifdef __GNUC__
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#pragma GCC diagnostic warning "-Wunused-variable"
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#endif
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/**
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Based on the Security Mode Selection, BIOS drives FORCE_PWR.
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@param[in] GpioNumber
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@param[in] Value
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**/
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VOID
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ForceDtbtPower(
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IN UINT8 GpioAccessType,
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IN UINT8 Expander,
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IN UINT32 GpioNumber,
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IN BOOLEAN Value
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);
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/**
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Get Security Level.
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@param[in] Bus Bus number for Host Router (DTBT)
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@param[in] Device Device number for Host Router (DTBT)
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@param[in] Function Function number for Host Router (DTBT)
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@param[in] Timeout Time out with 100 ms garnularity
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**/
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UINT8
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GetSecLevel (
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT8 Command,
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IN UINT32 Timeout
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);
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/**
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Set Security Level.
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@param[in] Data Security State
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@param[in] Bus Bus number for Host Router (DTBT)
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@param[in] Device Device number for Host Router (DTBT)
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@param[in] Function Function number for Host Router (DTBT)
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@param[in] Timeout Time out with 100 ms garnularity
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**/
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BOOLEAN
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SetSecLevel (
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IN UINT8 Data,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT8 Command,
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IN UINT32 Timeout
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);
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/**
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Execute TBT Mail Box Command
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@param[in] Command TBT Command
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@param[in] Bus Bus number for Host Router (DTBT)
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@param[in] Device Device number for Host Router (DTBT)
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@param[in] Function Function number for Host Router (DTBT)
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@param[in] Timeout Time out with 100 ms garnularity
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@Retval true if command executes succesfully
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**/
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BOOLEAN
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TbtSetPcie2TbtCommand(
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IN UINT8 Command,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT32 Timeout
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);
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/**
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Check connected TBT controller is supported or not by DeviceID
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@param[in] DeviceID DeviceID of of TBT controller
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@retval TRUE Valid DeviceID
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@retval FALSE Invalid DeviceID
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**/
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BOOLEAN
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IsTbtHostRouter (
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IN UINT16 DeviceID
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);
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/**
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Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Port physical Number
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@param[in] RpNumber Root port physical number. (0-based)
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@param[out] RpDev Return corresponding root port device number.
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@param[out] RpFun Return corresponding root port function number.
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@retval EFI_SUCCESS Root port device and function is retrieved
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**/
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EFI_STATUS
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EFIAPI
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GetDTbtRpDevFun(
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IN BOOLEAN Type,
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IN UINTN RpNumber,
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OUT UINTN *RpDev,
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OUT UINTN *RpFunc
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);
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/**
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Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
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@param[in] CommandOffsetAddress Tbt2Pcie Register Address
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@param[in] TimeOut Time out with 100 ms garnularity
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@param[in] Tbt2PcieDone Wait condition (wait for Bit to Clear/Set)
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@param[out] *Tbt2PcieValue Function Register value
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**/
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BOOLEAN
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InternalWaitforCommandCompletion (
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IN UINT64 CommandOffsetAddress,
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IN UINT32 TimeOut,
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IN BOOLEAN Tbt2PcieDone,
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OUT UINT32 *Tbt2PcieValue
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);
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VOID
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GetRootporttoSetResourcesforTbt (
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IN UINTN RpIndex,
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OUT UINT8 *RsvdExtraBusNum,
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OUT UINT16 *RsvdPcieMegaMem,
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OUT UINT8 *PcieMemAddrRngMax,
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OUT UINT16 *RsvdPciePMegaMem,
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OUT UINT8 *PciePMemAddrRngMax,
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OUT BOOLEAN *SetResourceforTbt
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);
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#endif
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