/** @file
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Provides silicon policy update library functions.
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Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <ConfigBlock.h>
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#include <SaPolicyCommon.h>
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#include <CpuPolicyCommon.h>
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#include <PchPreMemPolicyCommon.h>
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#include <Pi/PiFirmwareFile.h>
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#include <Register/Cpuid.h>
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#include <PchHsioPtssTables.h>
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#include <Library/PchInfoLib.h>
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#include <Library/SiliconPolicyUpdateLib.h>
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#include <Library/PcdLib.h>
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#include <Library/DebugLib.h>
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#include <Library/ConfigBlockLib.h>
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#include <Library/PeiLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/CpuPlatformLib.h>
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#include <Library/PchHsioLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <Library/MmPciLib.h>
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#include <Library/IoLib.h>
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//
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// Function prototypes
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//
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/**
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Performs the remainder of board-specific FSP Policy initialization.
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@param[in] Policy - Policy PPI pointer.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
|
EFI_STATUS
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EFIAPI
|
PeiFspBoardPolicyUpdatePreMem (
|
IN VOID *Policy
|
);
|
|
/**
|
Performs the remainder of board-specific FSP Policy initialization.
|
|
@param[in] Policy - Policy PPI pointer.
|
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
|
EFI_STATUS
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EFIAPI
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PeiFspBoardPolicyUpdate (
|
IN VOID *Policy
|
);
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/**
|
Get the next microcode patch pointer.
|
|
@param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found,
|
and output points to the next patch address found.
|
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@retval EFI_SUCCESS - Patch found.
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@retval EFI_NOT_FOUND - Patch not found.
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**/
|
EFI_STATUS
|
EFIAPI
|
RetrieveMicrocode (
|
IN OUT CPU_MICROCODE_HEADER **MicrocodeData
|
)
|
{
|
UINTN MicrocodeStart;
|
UINTN MicrocodeEnd;
|
UINTN TotalSize;
|
|
if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) {
|
return EFI_NOT_FOUND;
|
}
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|
///
|
/// Microcode binary in SEC
|
///
|
MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +
|
((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength +
|
sizeof (EFI_FFS_FILE_HEADER);
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MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize);
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if (*MicrocodeData == NULL) {
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*MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart;
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} else {
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if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) {
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DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n"));
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return EFI_NOT_FOUND;
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}
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TotalSize = (UINTN) ((*MicrocodeData)->TotalSize);
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if (TotalSize == 0) {
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TotalSize = 2048;
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}
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*MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize);
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if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) {
|
DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n"));
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return EFI_NOT_FOUND;
|
}
|
}
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return EFI_SUCCESS;
|
}
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/**
|
Get the microcode patch pointer.
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|
@retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found.
|
**/
|
EFI_PHYSICAL_ADDRESS
|
PlatformCpuLocateMicrocodePatch (
|
VOID
|
)
|
{
|
EFI_STATUS Status;
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CPU_MICROCODE_HEADER *MicrocodeData;
|
EFI_CPUID_REGISTER Cpuid;
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UINT32 UcodeRevision;
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UINTN MicrocodeBufferSize;
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VOID *MicrocodeBuffer = NULL;
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AsmCpuid (
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CPUID_VERSION_INFO,
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&Cpuid.RegEax,
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&Cpuid.RegEbx,
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&Cpuid.RegEcx,
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&Cpuid.RegEdx
|
);
|
|
UcodeRevision = GetCpuUcodeRevision ();
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MicrocodeData = NULL;
|
while (TRUE) {
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///
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/// Find the next patch address
|
///
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Status = RetrieveMicrocode (&MicrocodeData);
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DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData));
|
|
if (Status != EFI_SUCCESS) {
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break;
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} else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) {
|
break;
|
}
|
}
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|
if (EFI_ERROR (Status)) {
|
return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
|
}
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///
|
/// Check that microcode patch size is <= 128K max size,
|
/// then copy the patch from FV to temp buffer for faster access.
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///
|
MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize;
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if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) {
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MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize));
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if (MicrocodeBuffer != NULL) {
|
DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n"));
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CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize);
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|
return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer;
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} else {
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DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
|
}
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} else {
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DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n"));
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}
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return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
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}
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/**
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Update HSIO policy per board.
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|
@param[in] Policy - Policy PPI pointer (caller should ensure it is valid pointer)
|
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**/
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VOID
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InstallPlatformHsioPtssTable (
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IN VOID *Policy
|
)
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{
|
HSIO_PTSS_TABLES *UnknowPtssTables;
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HSIO_PTSS_TABLES *SpecificPtssTables;
|
HSIO_PTSS_TABLES *PtssTables;
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UINT8 PtssTableIndex;
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UINT32 UnknowTableSize;
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UINT32 SpecificTableSize;
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UINT32 TableSize;
|
UINT32 Entry;
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UINT8 LaneNum;
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UINT8 Index;
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UINT8 MaxSataPorts;
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UINT8 MaxPciePorts;
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UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
|
UINT8 PciePort;
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UINTN RpBase;
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UINTN RpDevice;
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UINTN RpFunction;
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UINT32 StrapFuseCfg;
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UINT8 PcieControllerCfg;
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PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;
|
PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;
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EFI_STATUS Status;
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Status = GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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UnknowPtssTables = NULL;
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UnknowTableSize = 0;
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SpecificPtssTables = NULL;
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SpecificTableSize = 0;
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|
if (GetPchGeneration () == SklPch) {
|
switch (PchStepping ()) {
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case PchLpB0:
|
case PchLpB1:
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UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1);
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UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1);
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SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size);
|
break;
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case PchLpC0:
|
case PchLpC1:
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UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2);
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UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2);
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SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size);
|
break;
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case PchHB0:
|
case PchHC0:
|
UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1);
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UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1);
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SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size);
|
break;
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case PchHD0:
|
case PchHD1:
|
UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
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UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
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SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
|
break;
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default:
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UnknowPtssTables = NULL;
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UnknowTableSize = 0;
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SpecificPtssTables = NULL;
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SpecificTableSize = 0;
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DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
|
}
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} else {
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switch (PchStepping ()) {
|
case KblPchHA0:
|
UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
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UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
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SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
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SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
|
break;
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default:
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UnknowPtssTables = NULL;
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UnknowTableSize = 0;
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SpecificPtssTables = NULL;
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SpecificTableSize = 0;
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DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
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}
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}
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PtssTableIndex = 0;
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MaxSataPorts = GetPchMaxSataPortNum ();
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MaxPciePorts = GetPchMaxPciePortNum ();
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ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
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//
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//Populate PCIe topology based on lane configuration
|
//
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for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
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Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);
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ASSERT_EFI_ERROR (Status);
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|
RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
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StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
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PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
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DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg));
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}
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for (Index = 0; Index < MaxPciePorts; Index++) {
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DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index]));
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}
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//
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//Case 1: BoardId is known, Topology is known/unknown
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//Case 1a: SATA
|
//
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PtssTables = SpecificPtssTables;
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TableSize = SpecificTableSize;
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for (Index = 0; Index < MaxSataPorts; Index++) {
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if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
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for (Entry = 0; Entry < TableSize; Entry++) {
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
|
)
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{
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PtssTableIndex++;
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
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HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
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HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) {
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if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
|
HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
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HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
|
}
|
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
|
HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
|
HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
|
}
|
} else {
|
ASSERT (FALSE);
|
}
|
}
|
}
|
}
|
}
|
//
|
//Case 1b: PCIe
|
//
|
for (Index = 0; Index < MaxPciePorts; Index++) {
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if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
|
for (Entry = 0; Entry < TableSize; Entry++) {
|
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
|
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
|
(PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
|
PtssTableIndex++;
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
|
HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE;
|
HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
|
|
} else {
|
ASSERT (FALSE);
|
}
|
}
|
}
|
}
|
}
|
//
|
//Case 2: BoardId is unknown, Topology is known/unknown
|
//
|
if (PtssTableIndex == 0) {
|
DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n"));
|
|
PtssTables = UnknowPtssTables;
|
TableSize = UnknowTableSize;
|
|
for (Index = 0; Index < MaxSataPorts; Index++) {
|
if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
|
for (Entry = 0; Entry < TableSize; Entry++) {
|
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
|
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
|
)
|
{
|
if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
|
HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
|
HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
|
|
} else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) {
|
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
|
HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
|
HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
|
|
}
|
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
|
HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
|
HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
|
}
|
} else {
|
ASSERT (FALSE);
|
}
|
}
|
}
|
}
|
}
|
for (Index = 0; Index < MaxPciePorts; Index++) {
|
if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
|
for (Entry = 0; Entry < TableSize; Entry++) {
|
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
|
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
|
(PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
|
if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
|
HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE;
|
HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
|
} else {
|
ASSERT (FALSE);
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
/**
|
Update PreMem phase silicon policy per board.
|
|
@param[in] Policy - Policy PPI pointer.
|
|
@retval Policy - Policy PPI pointer.
|
|
**/
|
VOID *
|
EFIAPI
|
SiliconPolicyUpdatePreMem (
|
IN VOID *Policy
|
)
|
{
|
EFI_STATUS Status;
|
SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
|
MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
|
VOID *Buffer;
|
UINTN VariableSize;
|
VOID *MemorySavedData;
|
UINT8 SpdAddressTable[4];
|
|
DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n"));
|
|
if (Policy != NULL) {
|
SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0);
|
SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1);
|
SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2);
|
SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3);
|
|
MiscPeiPreMemConfig = NULL;
|
Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
|
ASSERT_EFI_ERROR (Status);
|
|
if (MiscPeiPreMemConfig != NULL) {
|
//
|
// Pass board specific SpdAddressTable to policy
|
//
|
CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) SpdAddressTable, (sizeof (UINT8) * 4));
|
|
//
|
// Set size of SMRAM
|
//
|
MiscPeiPreMemConfig->TsegSize = PcdGet32 (PcdTsegSize);
|
|
//
|
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
|
// Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI added in FSP 2.1, hence
|
// the platform specific S3DataPtr must be used instead.
|
//
|
VariableSize = 0;
|
MemorySavedData = NULL;
|
Status = PeiGetVariable (
|
L"MemoryConfig",
|
&gFspNonVolatileStorageHobGuid,
|
&MemorySavedData,
|
&VariableSize
|
);
|
DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status));
|
DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));
|
if (!EFI_ERROR (Status)) {
|
MiscPeiPreMemConfig->S3DataPtr = MemorySavedData;
|
}
|
|
//
|
// In FSP Dispatch Mode these BAR values are initialized by SiliconPolicyInitPreMem() in
|
// KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c; this function calls
|
// PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI->PeiPreMemPolicyInit() to initialize all Config Blocks
|
// with default policy values (including these BAR values.) PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
|
// is implemented in the FSP. Make sure the value that FSP is using matches the value we are using.
|
//
|
ASSERT (PcdGet64 (PcdMchBaseAddress) <= 0xFFFFFFFF);
|
ASSERT (MiscPeiPreMemConfig->MchBar == (UINT32) PcdGet64 (PcdMchBaseAddress));
|
ASSERT (MiscPeiPreMemConfig->SmbusBar == PcdGet16 (PcdSmbusBaseAddress));
|
}
|
MemConfigNoCrc = NULL;
|
Status = GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
|
ASSERT_EFI_ERROR (Status);
|
|
if (MemConfigNoCrc != NULL) {
|
MemConfigNoCrc->PlatformMemorySize = PcdGet32 (PcdPeiMinMemorySize);
|
|
//
|
// Only if SpdAddressTables are all zero we need to pass hard-coded SPD data buffer.
|
// Otherwise FSP will retrieve SPD from DIMM basing on SpdAddressTables policy.
|
//
|
if (*((UINT32 *) (UINTN) SpdAddressTable) == 0) {
|
DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n"));
|
CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
|
CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
|
}
|
|
DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
|
Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
|
if (Buffer) {
|
CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], Buffer, 12);
|
CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], (UINT8*) Buffer + 12, 12);
|
}
|
Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
|
if (Buffer) {
|
CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[0], Buffer, 8);
|
CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[1], (UINT8*) Buffer + 8, 8);
|
}
|
|
DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
|
Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
|
if (Buffer) {
|
CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompResistor[0]), Buffer, 6);
|
}
|
Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
|
if (Buffer) {
|
CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompTarget[0]), Buffer, 10);
|
}
|
}
|
//
|
// Update PCD policy
|
//
|
InstallPlatformHsioPtssTable (Policy);
|
|
// Board-specific policy overrides
|
PeiFspBoardPolicyUpdatePreMem (Policy);
|
}
|
|
return Policy;
|
}
|
|
/**
|
Update PostMem phase silicon policy per board.
|
|
@param[in] Policy - Policy PPI pointer.
|
|
@retval Policy - Policy PPI pointer.
|
|
**/
|
VOID *
|
EFIAPI
|
SiliconPolicyUpdatePostMem (
|
IN VOID *Policy
|
)
|
{
|
EFI_STATUS Status;
|
VOID *Buffer;
|
VOID *MemBuffer;
|
UINT32 Size;
|
GRAPHICS_PEI_CONFIG *GtConfig;
|
CPU_CONFIG *CpuConfig;
|
|
DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));
|
|
GtConfig = NULL;
|
Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
|
ASSERT_EFI_ERROR (Status);
|
|
if (GtConfig != NULL) {
|
//
|
// Always enable PEI graphics initialization.
|
//
|
GtConfig->PeiGraphicsPeimInit = 1;
|
Size = 0;
|
Buffer = NULL;
|
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
|
if (Buffer == NULL) {
|
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
|
} else {
|
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
|
if ((MemBuffer != NULL) && (Buffer != NULL)) {
|
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
|
GtConfig->GraphicsConfigPtr = MemBuffer;
|
} else {
|
DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
|
GtConfig->GraphicsConfigPtr = 0;
|
}
|
}
|
DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr));
|
DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
|
Size = 0;
|
Buffer = NULL;
|
PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);
|
if (Buffer == NULL) {
|
DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
|
} else {
|
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
|
if ((MemBuffer != NULL) && (Buffer != NULL)) {
|
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
|
GtConfig->LogoPtr = MemBuffer;
|
GtConfig->LogoSize = Size;
|
} else {
|
DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
|
GtConfig->LogoPtr = 0;
|
GtConfig->LogoSize = 0;
|
}
|
}
|
DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoPtr));
|
DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoSize));
|
}
|
|
CpuConfig = NULL;
|
Status = GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID *)&CpuConfig);
|
ASSERT_EFI_ERROR (Status);
|
|
if (CpuConfig != NULL) {
|
CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch ();
|
}
|
|
if (Policy != NULL) {
|
// Board-specific policy overrides
|
PeiFspBoardPolicyUpdate (Policy);
|
}
|
return Policy;
|
}
|
|
/**
|
Update late phase silicon policy per board.
|
|
@param[in] Policy - Policy PPI pointer.
|
|
@retval Policy - Policy PPI pointer.
|
|
**/
|
VOID *
|
EFIAPI
|
SiliconPolicyUpdateLate (
|
IN VOID *Policy
|
)
|
{
|
return Policy;
|
}
|
