/** @file
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This file configures Aspire VN7-572G board-specific policies.
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Copyright (c) 2021, Baruch Binyamin Doron
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <ConfigBlock.h>
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#include <Library/ConfigBlockLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <CpuPolicyCommon.h>
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#include <PchPolicyCommon.h>
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#include <PchPreMemPolicyCommon.h>
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#include <SaPolicyCommon.h>
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/* FIXME/NB: Bring back in-line with API mode policies */
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#define SA_VR 0
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#define IA_VR 1
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#define GT_UNSLICED_VR 2
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#define GT_SLICED_VR 3
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/**
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Performs the remainder of board-specific FSP Policy initialization.
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@param[in] Policy Policy PPI pointer.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
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EFI_STATUS
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EFIAPI
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PeiFspBoardPolicyUpdatePreMem (
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IN VOID *Policy
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)
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{
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EFI_STATUS Status;
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SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
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MEMORY_CONFIGURATION *MemConfig;
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PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig;
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// Retrieve the config blocks we depend on
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Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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if (MiscPeiPreMemConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gMemoryConfigGuid, (VOID *) &MemConfig);
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ASSERT_EFI_ERROR (Status);
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if (MemConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gHpetPreMemConfigGuid, (VOID *) &HpetPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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if (HpetPreMemConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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/* System Agent config */
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MiscPeiPreMemConfig->UserBd = PcdGet8(PcdSaMiscUserBd);
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MemConfig->DqPinsInterleaved = (UINT8)PcdGetBool(PcdMrcDqPinsInterleaved);
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MemConfig->CaVrefConfig = PcdGet8(PcdMrcCaVrefConfig);
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MemConfig->SaGv = 3; // Enabled
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// TODO: Why should this be here?
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// FSP should program it's default BDF value (but where is bus 0xF0?)
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HpetPreMemConfig->BdfValid = 1;
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/* iGFX config */
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//FIXME FspmUpd->FspmConfig.PrimaryDisplay = 4; // Switchable Graphics
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return EFI_SUCCESS;
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}
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/**
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Performs the remainder of board-specific FSP Policy initialization.
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@param[in] Policy Policy PPI pointer.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
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EFI_STATUS
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EFIAPI
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PeiFspBoardPolicyUpdate (
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IN VOID *Policy
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)
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{
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EFI_STATUS Status;
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PCH_LOCK_DOWN_CONFIG *LockDownConfig;
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PCH_GENERAL_CONFIG *PchGeneralConfig;
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CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig;
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CPU_POWER_MGMT_VR_CONFIG *CpuPowerMgmtVrConfig;
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PCH_USB_CONFIG *UsbConfig;
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PCH_SATA_CONFIG *SataConfig;
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PCH_PCIE_CONFIG *PchPcieConfig;
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PCH_PM_CONFIG *PmConfig;
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PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
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PCH_HDAUDIO_CONFIG *HdAudioConfig;
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PCH_IOAPIC_CONFIG *IoApicConfig;
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INTN Index;
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// Retrieve the config blocks we depend on (all are expected to be installed)
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Status = GetConfigBlock (Policy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
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ASSERT_EFI_ERROR (Status);
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if (LockDownConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
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ASSERT_EFI_ERROR (Status);
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if (PchGeneralConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig);
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ASSERT_EFI_ERROR (Status);
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if (CpuPowerMgmtBasicConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gCpuPowerMgmtVrConfigGuid, (VOID *) &CpuPowerMgmtVrConfig);
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ASSERT_EFI_ERROR (Status);
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if (CpuPowerMgmtVrConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gUsbConfigGuid, (VOID *) &UsbConfig);
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ASSERT_EFI_ERROR (Status);
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if (UsbConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gSataConfigGuid, (VOID *) &SataConfig);
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ASSERT_EFI_ERROR (Status);
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if (SataConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gPcieRpConfigGuid, (VOID *) &PchPcieConfig);
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ASSERT_EFI_ERROR (Status);
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if (PchPcieConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gPmConfigGuid, (VOID *) &PmConfig);
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ASSERT_EFI_ERROR (Status);
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if (PmConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gSerialIrqConfigGuid, (VOID *) &SerialIrqConfig);
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ASSERT_EFI_ERROR (Status);
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if (SerialIrqConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
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ASSERT_EFI_ERROR (Status);
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if (HdAudioConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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Status = GetConfigBlock (Policy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
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ASSERT_EFI_ERROR (Status);
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if (IoApicConfig == NULL) {
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return EFI_NOT_FOUND;
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}
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// FIXME/NB: This is insecure and not production-ready!
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// TODO: Configure SPI lockdown by variable on FrontPage?
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LockDownConfig->BiosLock = 0;
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LockDownConfig->SpiEiss = 0;
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// TODO: Why should this be here?
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// FSP should program it's default BDF value (but where is bus 0xF0?)
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IoApicConfig->BdfValid = 1;
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// Note: SerialIoDevMode default is satisfactory, but not entirely accurate.
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// Board has no GPIO expander on I2C4 (despite SetupUtility claim
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// that it does - this appears to be static text?) and is UART0 merely supporting
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// the UART2 devfn?
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// Acer IDs (TODO: "Newgate" IDs)
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//FIXME FspsUpd->FspsConfig.DefaultSvid = 0x1025;
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//FIXME FspsUpd->FspsConfig.DefaultSid = 0x1037;
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PchGeneralConfig->SubSystemVendorId = 0x1025;
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PchGeneralConfig->SubSystemId = 0x1037;
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/* System Agent config */
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// Set the Thermal Control Circuit (TCC) activation value to 97C
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// even though FSP integration guide says to set it to 100C for SKL-U
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// (offset at 0), because when the TCC activates at 100C, the CPU
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// will have already shut itself down from overheating protection.
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CpuPowerMgmtBasicConfig->TccActivationOffset = 3;
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// VR Slew rate setting for improving audible noise
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CpuPowerMgmtVrConfig->AcousticNoiseMitigation = 1;
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CpuPowerMgmtVrConfig->SlowSlewRateForIa = 3; // Fast/16
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CpuPowerMgmtVrConfig->SlowSlewRateForGt = 3; // Fast/16
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CpuPowerMgmtVrConfig->SlowSlewRateForSa = 0; // Fast/2
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CpuPowerMgmtVrConfig->FastPkgCRampDisableIa = 0;
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CpuPowerMgmtVrConfig->FastPkgCRampDisableGt = 0;
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CpuPowerMgmtVrConfig->FastPkgCRampDisableSa = 0;
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// VR domain configuration (copied from board port, before VR config moved
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// to SoC. Should match SKL-U (GT2, 15W) in the SKL-U datasheet, vol. 1
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CpuPowerMgmtVrConfig->AcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
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CpuPowerMgmtVrConfig->DcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
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CpuPowerMgmtVrConfig->Psi1Threshold[SA_VR] = 80; // 20A (in 1/4 increments)
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CpuPowerMgmtVrConfig->Psi2Threshold[SA_VR] = 16; // 4A (in 1/4 increments)
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CpuPowerMgmtVrConfig->Psi3Threshold[SA_VR] = 4; // 1A (in 1/4 increments)
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CpuPowerMgmtVrConfig->IccMax[SA_VR] = 18; // 4.5A (in 1/4 increments)
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CpuPowerMgmtVrConfig->VrVoltageLimit[SA_VR] = 1520; // 1520mV
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CpuPowerMgmtVrConfig->AcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
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CpuPowerMgmtVrConfig->DcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
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CpuPowerMgmtVrConfig->Psi1Threshold[IA_VR] = 80; // 20A (in 1/4 increments)
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CpuPowerMgmtVrConfig->Psi2Threshold[IA_VR] = 20; // 5A (in 1/4 increments)
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CpuPowerMgmtVrConfig->Psi3Threshold[IA_VR] = 4; // 1A (in 1/4 increments)
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CpuPowerMgmtVrConfig->IccMax[IA_VR] = 116; // 29A (in 1/4 increments)
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CpuPowerMgmtVrConfig->VrVoltageLimit[IA_VR] = 1520; // 1520mV
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CpuPowerMgmtVrConfig->AcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
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CpuPowerMgmtVrConfig->DcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
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CpuPowerMgmtVrConfig->Psi1Threshold[GT_UNSLICED_VR] = 80; // 20A (in 1/4 increments)
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CpuPowerMgmtVrConfig->Psi2Threshold[GT_UNSLICED_VR] = 20; // 5A (in 1/4 increments)
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CpuPowerMgmtVrConfig->Psi3Threshold[GT_UNSLICED_VR] = 4; // 1A (in 1/4 increments)
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CpuPowerMgmtVrConfig->IccMax[GT_UNSLICED_VR] = 124; // 31A (in 1/4 increments)
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CpuPowerMgmtVrConfig->VrVoltageLimit[GT_UNSLICED_VR] = 1520; // 1520mV
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CpuPowerMgmtVrConfig->AcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
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CpuPowerMgmtVrConfig->DcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
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CpuPowerMgmtVrConfig->Psi1Threshold[GT_SLICED_VR] = 80; // 20A (in 1/4 increments)
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CpuPowerMgmtVrConfig->Psi2Threshold[GT_SLICED_VR] = 20; // 5A (in 1/4 increments)
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CpuPowerMgmtVrConfig->Psi3Threshold[GT_SLICED_VR] = 4; // 1A (in 1/4 increments)
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CpuPowerMgmtVrConfig->IccMax[GT_SLICED_VR] = 124; // 31A (in 1/4 increments)
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CpuPowerMgmtVrConfig->VrVoltageLimit[GT_SLICED_VR] = 1520; // 1520mV
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// PL1, PL2 override 35W, PL4 override 43W (in 125 mW increments)
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CpuPowerMgmtBasicConfig->PowerLimit1 = 280;
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CpuPowerMgmtBasicConfig->PowerLimit2Power = 280;
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CpuPowerMgmtBasicConfig->PowerLimit4 = 344;
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// ISL95857 VR
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// Send VR specific command for PS4 exit issue
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CpuPowerMgmtVrConfig->SendVrMbxCmd1 = 2;
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// Send VR mailbox command for IA/GT/SA rails
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//FIXME FspsUpd->FspsConfig.IslVrCmd = 2;
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/* Skycam config */
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// FspsUpd->FspsConfig.SaImguEnable = 0;
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// FspsUpd->FspsConfig.PchCio2Enable = 0;
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/* Sensor hub config */
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// FspsUpd->FspsConfig.PchIshEnable = 0;
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/* xHCI config */
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// FspsUpd->FspsConfig.SsicPortEnable = 0;
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// Configure USB2 ports in two blocks
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for (Index = 0; Index < 3; Index++) {
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UsbConfig->PortUsb20[Index].Afe.Txiset = 0x2; // 16.9mV
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UsbConfig->PortUsb20[Index].Afe.Predeemp = 1; // De-emphasis on
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UsbConfig->PortUsb20[Index].Afe.Petxiset = 0x3;// 28.15mV
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UsbConfig->PortUsb20[Index].Afe.Pehalfbit = 1; // Half-bit
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}
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for (Index = 3; Index < 9; Index++) {
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UsbConfig->PortUsb20[Index].Afe.Txiset = 0; // 0mV
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UsbConfig->PortUsb20[Index].Afe.Predeemp = 0x2;// Pre-emphasis and de-emphasis on
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UsbConfig->PortUsb20[Index].Afe.Petxiset = 0x7;// 56.3mV
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UsbConfig->PortUsb20[Index].Afe.Pehalfbit = 1; // Half-bit
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}
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// Configure all USB3 ports
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for (Index = 0; Index < 4; Index++) {
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UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable = 1;
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UsbConfig->PortUsb30[Index].HsioTxDeEmph = 0x29; // Default (approximately -3.5dB de-emphasis)
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}
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// Disable all OC pins
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for (Index = 0; Index < 9; Index++) {
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UsbConfig->PortUsb20[Index].OverCurrentPin = PchUsbOverCurrentPinSkip;
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}
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for (Index = 0; Index < 4; Index++) {
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UsbConfig->PortUsb30[Index].OverCurrentPin = PchUsbOverCurrentPinSkip;
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}
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/* xDCI config */
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// FspsUpd->FspsConfig.XdciEnable = 0;
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/* SATA config */
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// This is a hard silicon requirement, discovered several times by coreboot boards
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SataConfig->PwrOptEnable = 1;
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/* PCIe config */
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// Port 1 (dGPU; x4)
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PchPcieConfig->RootPort[0].AdvancedErrorReporting = 1;
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PchPcieConfig->RootPort[0].LtrEnable = 1;
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PchPcieConfig->RootPort[0].ClkReqSupported = 1;
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PchPcieConfig->RootPort[0].ClkReqNumber = 0x0;
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PchPcieConfig->RootPort[0].MaxPayload = PchPcieMaxPayload256;
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// Port 7 (NGFF; x2)
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PchPcieConfig->RootPort[6].AdvancedErrorReporting = 1;
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PchPcieConfig->RootPort[6].LtrEnable = 1;
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PchPcieConfig->RootPort[6].ClkReqSupported = 1;
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PchPcieConfig->RootPort[6].ClkReqNumber = 0x3;
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PchPcieConfig->RootPort[6].MaxPayload = PchPcieMaxPayload256;
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// Port 9 (LAN)
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PchPcieConfig->RootPort[8].AdvancedErrorReporting = 1;
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PchPcieConfig->RootPort[8].LtrEnable = 1;
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PchPcieConfig->RootPort[8].ClkReqSupported = 1;
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PchPcieConfig->RootPort[8].ClkReqNumber = 0x1;
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PchPcieConfig->RootPort[8].MaxPayload = PchPcieMaxPayload256;
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// Port 10 (WLAN)
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PchPcieConfig->RootPort[9].AdvancedErrorReporting = 1;
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PchPcieConfig->RootPort[9].LtrEnable = 1;
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PchPcieConfig->RootPort[9].ClkReqSupported = 1;
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PchPcieConfig->RootPort[9].ClkReqNumber = 0x2;
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PchPcieConfig->RootPort[9].MaxPayload = PchPcieMaxPayload256;
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// ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors)
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PchPcieConfig->RootPort[9].Aspm = PchPcieAspmL1;
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/* LPC config */
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// EC/KBC requires continuous mode
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PmConfig->LpcClockRun = 1;
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SerialIrqConfig->SirqMode = PchContinuousMode;
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/* HDA config */
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HdAudioConfig->DspEndpointDmic = PchHdaDmic1chArray;
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/* SCS config */
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// Although platform NVS area shows this enabled, the SD card reader is connected over USB, not SCS
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// FspsUpd->FspsConfig.ScsEmmcEnabled = 0;
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// FspsUpd->FspsConfig.ScsSdCardEnabled = 0;
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return EFI_SUCCESS;
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}
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