## @file
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# FDF file of Platform.
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#
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# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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!include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
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################################################################################
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#
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# FD Section
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# The [FD] Section is made up of the definition statements and a
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# description of what goes into the Flash Device Image. Each FD section
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# defines one flash "device" image. A flash device image may be one of
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# the following: Removable media bootable image (like a boot floppy
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# image,) an Option ROM image (that would be "flashed" into an add-in
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# card,) a System "Flash" image (that would be burned into a system's
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# flash) or an Update ("Capsule") image that will be used to update and
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# existing system flash.
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#
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################################################################################
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[FD.AspireVn7Dash572G]
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#
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# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
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# assigned with PCD values. Instead, it uses the definitions for its variety, which
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# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
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#
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BaseAddress = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the FLASH Device.
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Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize #The size in bytes of the FLASH Device
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ErasePolarity = 1
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BlockSize = $(FLASH_BLOCK_SIZE)
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NumBlocks = $(FLASH_NUM_BLOCKS)
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DEFINE SIPKG_DXE_SMM_BIN = INF
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DEFINE SIPKG_PEI_BIN = INF
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# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
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# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
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SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
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SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
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SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
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SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
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SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
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SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
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SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
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SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
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SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
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SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
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SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
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SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
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SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
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SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
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SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
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SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
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################################################################################
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#
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# Following are lists of FD Region layout which correspond to the locations of different
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# images within the flash device.
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#
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# Regions must be defined in ascending order and may not overlap.
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#
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# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
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# the pipe "|" character, followed by the size of the region, also in hex with the leading
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# "0x" characters. Like:
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# Offset|Size
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# PcdOffsetCName|PcdSizeCName
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# RegionType <FV, DATA, or FILE>
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# Fv Size can be adjusted
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#
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################################################################################
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gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
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#NV_VARIABLE_STORE
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DATA = {
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## This is the EFI_FIRMWARE_VOLUME_HEADER
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# ZeroVector []
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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# FileSystemGuid
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0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
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0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
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# FvLength: 0x40000
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0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
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#Signature "_FVH" #Attributes
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0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
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#HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
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#
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# Be careful on CheckSum field.
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#
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0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
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#Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
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0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
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#Blockmap[1]: End
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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## This is the VARIABLE_STORE_HEADER
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!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
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# Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
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0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
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0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
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!else
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# Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
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0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
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0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
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!endif
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#Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
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# This can speed up the Variable Dispatch a bit.
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0xB8, 0xDF, 0x01, 0x00,
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#FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
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0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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}
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gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
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#NV_FTW_WORKING
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DATA = {
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# EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
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# { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
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0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
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0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
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# Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
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0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
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# WriteQueueSize: UINT64
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0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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}
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gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
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#NV_FTW_SPARE
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gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize
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gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageBase|gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize
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#DEBUG_MESSAGE_AREA
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
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FV = FvAdvanced
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
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FV = FvSecurity
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
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FV = FvOsBoot
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
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FV = FvUefiBoot
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
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FV = FvPostMemory
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gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
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gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
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#Microcode
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FV = FvMicrocode
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
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# FSP_S Section
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FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
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# FSP_M Section
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FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
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# FSP_T Section
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FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
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FV = FvAdvancedPreMemory
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
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gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
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FV = FvPreMemory
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################################################################################
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#
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# FV Section
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#
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# [FV] section is used to define what components or modules are placed within a flash
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# device file. This section also defines order the components and modules are positioned
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# within the image. The [FV] section consists of define statements, set statements and
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# module statements.
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#
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################################################################################
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[FV.FvMicrocode]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = FALSE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = FALSE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
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[FV.FvPreMemory]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
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INF UefiCpuPkg/SecCore/SecCore.inf
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!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
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#
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# PeiMain is needed only for FSP API mode or EDK2 build,
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# in FSP dispatch mode the one inside FSP Binary is launched
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# unless requested otherwise (PcdFspDispatchModeUseFspPeiMain == FALSE).
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#
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INF MdeModulePkg/Core/Pei/PeiMain.inf
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!endif
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!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
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INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
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INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
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INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
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INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
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INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
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[FV.FvPostMemoryUncompact]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
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!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
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# Init Board Config PCD
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INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
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INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
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INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
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!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
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FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {
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SECTION RAW = $(BOARD)/Vbt.bin
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SECTION UI = "Vbt"
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}
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FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
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SECTION RAW = MdeModulePkg/Logo/Logo.bmp
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}
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!endif # PcdPeiDisplayEnable
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[FV.FvPostMemory]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
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FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
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SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
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SECTION FV_IMAGE = FvPostMemoryUncompact
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}
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}
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[FV.FvUefiBootUncompact]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
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# NOTE: UefiDriverEntryPoint imports a dependency on the architectural protocols.
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APRIORI DXE {
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INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
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INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
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INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
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}
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!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
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INF UefiCpuPkg/CpuDxe/CpuDxe.inf
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INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
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INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
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INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
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INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
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INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
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INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
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INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
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INF MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
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INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
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INF ShellPkg/Application/Shell/Shell.inf
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INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
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!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
|
#
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# Below module is used by FSP API mode
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#
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INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
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!endif
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|
INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
|
|
[FV.FvUefiBoot]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
|
FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
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FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
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SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
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SECTION FV_IMAGE = FvUefiBootUncompact
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}
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}
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|
[FV.FvOsBootUncompact]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
|
FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
|
|
# NOTE: UefiDriverEntryPoint imports a dependency on the architectural protocols.
|
APRIORI DXE {
|
INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
|
INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
|
}
|
|
!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
|
|
INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
|
|
!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
|
INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
|
INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
|
INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
|
|
INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
|
INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
|
|
INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
|
INF RuleOverride = ACPITABLE $(PROJECT)/Acpi/BoardAcpiTables.inf
|
|
INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
|
|
!endif
|
|
[FV.FvLateSilicon]
|
BlockSize = $(FLASH_BLOCK_SIZE)
|
FvAlignment = 16
|
ERASE_POLARITY = 1
|
MEMORY_MAPPED = TRUE
|
STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
|
READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
|
READ_LOCK_CAP = TRUE
|
READ_LOCK_STATUS = TRUE
|
FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
|
|
!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
|
$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf
|
$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
|
|
$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
|
|
$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
|
$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
|
$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
|
$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
|
|
INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
|
INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
|
|
!endif
|
|
[FV.FvOsBoot]
|
BlockSize = $(FLASH_BLOCK_SIZE)
|
FvAlignment = 16
|
ERASE_POLARITY = 1
|
MEMORY_MAPPED = TRUE
|
STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
|
READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
|
READ_LOCK_CAP = TRUE
|
READ_LOCK_STATUS = TRUE
|
FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
|
|
FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
|
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
|
SECTION FV_IMAGE = FvOsBootUncompact
|
}
|
}
|
|
FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
|
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
|
SECTION FV_IMAGE = FvLateSilicon
|
}
|
}
|
|
[FV.FvSecurityPreMemory]
|
BlockSize = $(FLASH_BLOCK_SIZE)
|
FvAlignment = 16 #FV alignment and FV attributes setting.
|
ERASE_POLARITY = 1
|
MEMORY_MAPPED = TRUE
|
STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
|
READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
|
READ_LOCK_CAP = TRUE
|
READ_LOCK_STATUS = TRUE
|
FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
|
|
!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
|
|
INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
|
|
INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
|
|
[FV.FvSecurityPostMemory]
|
BlockSize = $(FLASH_BLOCK_SIZE)
|
FvAlignment = 16 #FV alignment and FV attributes setting.
|
ERASE_POLARITY = 1
|
MEMORY_MAPPED = TRUE
|
STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
|
READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
|
READ_LOCK_CAP = TRUE
|
READ_LOCK_STATUS = TRUE
|
FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
|
|
!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
|
|
!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
|
INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
|
!endif
|
|
[FV.FvSecurityLate]
|
BlockSize = $(FLASH_BLOCK_SIZE)
|
FvAlignment = 16
|
ERASE_POLARITY = 1
|
MEMORY_MAPPED = TRUE
|
STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
|
READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
|
READ_LOCK_CAP = TRUE
|
READ_LOCK_STATUS = TRUE
|
FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
|
|
!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
|
|
INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
|
|
!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
|
|
INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf
|
|
!endif
|
|
!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
|
|
INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
|
|
!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
|
INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
|
!endif
|
|
!endif
|
|
[FV.FvSecurity]
|
BlockSize = $(FLASH_BLOCK_SIZE)
|
FvAlignment = 16
|
ERASE_POLARITY = 1
|
MEMORY_MAPPED = TRUE
|
STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
|
READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
|
READ_LOCK_CAP = TRUE
|
READ_LOCK_STATUS = TRUE
|
FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
|
|
FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
|
SECTION FV_IMAGE = FvSecurityPreMemory
|
}
|
|
FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
|
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
|
SECTION FV_IMAGE = FvSecurityPostMemory
|
}
|
}
|
|
FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
|
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
|
SECTION FV_IMAGE = FvSecurityLate
|
}
|
}
|
|
#
|
# Pre-memory Advanced Features
|
#
|
[FV.FvAdvancedPreMemory]
|
FvAlignment = 16
|
ERASE_POLARITY = 1
|
MEMORY_MAPPED = TRUE
|
STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
|
READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
|
READ_LOCK_CAP = TRUE
|
READ_LOCK_STATUS = TRUE
|
FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
|
|
!include AdvancedFeaturePkg/Include/PreMemory.fdf
|
|
!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
|
INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
|
!endif
|
|
#
|
# Post-Memory Advanced Features
|
#
|
[FV.FvAdvancedUncompact]
|
FvAlignment = 16
|
ERASE_POLARITY = 1
|
MEMORY_MAPPED = TRUE
|
STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
|
READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
|
READ_LOCK_CAP = TRUE
|
READ_LOCK_STATUS = TRUE
|
FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
|
|
!include AdvancedFeaturePkg/Include/PostMemory.fdf
|
|
!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
|
INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
|
INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
|
INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
|
!endif
|
|
#
|
# Compressed FV with Post-Memory Advanced Features
|
#
|
[FV.FvAdvanced]
|
BlockSize = $(FLASH_BLOCK_SIZE)
|
FvAlignment = 16
|
ERASE_POLARITY = 1
|
MEMORY_MAPPED = TRUE
|
STICKY_WRITE = TRUE
|
LOCK_CAP = TRUE
|
LOCK_STATUS = TRUE
|
WRITE_DISABLED_CAP = TRUE
|
WRITE_ENABLED_CAP = TRUE
|
WRITE_STATUS = TRUE
|
WRITE_LOCK_CAP = TRUE
|
WRITE_LOCK_STATUS = TRUE
|
READ_DISABLED_CAP = TRUE
|
READ_ENABLED_CAP = TRUE
|
READ_STATUS = TRUE
|
READ_LOCK_CAP = TRUE
|
READ_LOCK_STATUS = TRUE
|
FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
|
|
FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
|
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
|
SECTION FV_IMAGE = FvAdvancedUncompact
|
}
|
}
|
|
################################################################################
|
#
|
# Rules are use with the [FV] section's module INF type to define
|
# how an FFS file is created for a given INF file. The following Rule are the default
|
# rules for the different module type. User can add the customized rules to define the
|
# content of the FFS file.
|
#
|
################################################################################
|
|
!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
|
